Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-04-24
2001-09-11
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C326S016000
Reexamination Certificate
active
06289480
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to scan design for test (DFT) and, in particular, to circuitry and methods for handling high impedance conditions in integrated circuits when implementing scan DFT.
2. Discussion of the Related Art
“Testability” is an integrated circuit device design characteristic that influences various costs associated with testing the device. Usually, testability allows for determination of the status of a device, quick isolation of faults within the device, and cost-effective development of the tests themselves to determine device status.
“Design for Test” (DFT) techniques are design efforts specifically employed to ensure that a device is testable.
Two important attributes related to device testability are “controllability” and “observability.” “Controllabilty” is the ability to establish a specific signal value at each node in a circuit by setting values on the circuit's inputs. “Observability” is the ability to determine the signal value at a node in a circuit by controlling the circuit's inputs and observing its outputs.
One of the most popular DFT techniques is referred to as scan design since it utilizes scan registers. A scan register is a register with both shift and parallel-load capability. The storage cells in a scan register are used as test control and/or observation points.
FIG. 1
shows a conventional scan storage cell (SSC) register chain. When TE=0 (normal mode), data are loaded into the individual scan storage cell registers
10
in parallel from associated data input lines D based upon clock signal CK. When TE=1 (test mode), data are loaded serially into the scan chain from a test line Si based upon clock signal CK. Thus, a scan register shifts test data when TE=1 and loads normal data in parallel when TE=0. Loading test data into a scan register chain when TE=1 is referred to as a scan-in operation. Reading data out of a scan register chain is referred to as a scan-out operation.
One problem associated with scan DFT is that it limits circuit designers to a very restrictive design style to the exclusion of other design practices, styles and techniques. One such restriction is a strict prohibition on the use of high impedance busses in the circuit.
However, for a variety of reasons, it is strategically desirable for integrated circuit designers to have the capability to include high impedance conditions on their devices, since it is an important design tool that is extremely useful and is widely used. The problem arises because, when test data is being shifted into a scan chain, the situation could arise in which multiple drivers
14
are attempting to drive a bus
16
, as shown in
FIG. 1
, with clear undesirable consequences.
Therefore, it would be desirable to have available a scan design for test technique that enables the use of high impedance busses in the circuit design.
SUMMARY OF THE INVENTION
The present invention provides circuitry and methods for handling high impedance busses in a scan implementation by preventing all control signals to bus driver circuits from getting through to the drivers during a scan operation.
Thus, in accordance with the concepts of the present invention, an integrated circuit includes a plurality of bus driver circuits. Each bus driver circuit has a driver output connected to a bus to provide an associated driver output signal to the bus. Each bus driver circuit also includes a high impedance control node. An input control signal having the first logic state applied to the control node enables the bus driver circuit to provide an associated driver output signal having either a high logic state or a low logic state. An input control signal having a second logic state applied to the control node causes the bus driver circuit to provide an associated driver output signal having a high impedance state. The integrated circuit also includes a plurality of scan registers connected as part of a scan chain. The scan chain responds to a scan test enable signal having the second logic state by initiating a scan-in operation in which test data is sequentially shifted into the scan chain. Each one of the scan registers has an output coupled to a data input of a corresponding one of the bus driver circuits. High impedance control circuitry responds to the second logic state of the scan test enable signal by applying an input control signal having the second logic state to the control node of each of the plurality of bus driver circuits. Thus, during a scan operation, the bus is held in a high impedance state.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.
REFERENCES:
patent: 4703484 (1987-10-01), Rolfe et al.
patent: 5852617 (1998-12-01), Mote, Jr.
patent: 5909452 (1999-06-01), Angelotti
patent: 5983376 (1999-11-01), Narayanan
Angelotti et al.(System Level Interconnect Test in a Tristate Environment.IEEE, Oct. 1993).
Lamarre Guy
National Semiconductor Corporation
Stallman & Pollock LLP
Tu Christine T.
LandOfFree
Circuitry for handling high impedance busses in a scan... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuitry for handling high impedance busses in a scan..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuitry for handling high impedance busses in a scan... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2512305