Clock transferring apparatus, and testing apparatus

Details Clock transferring apparatus, and testing apparatus Clock transferring apparatus, and testing apparatus

2006-08-11

2009-06-16

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S707000, C714S715000, C714S724000, C714S731000, C714S738000, C714S814000, C702S069000, C702S117000, C713S400000, C713S500000, C324S765010, C375S371000

Reexamination Certificate

active

07549101

ABSTRACT:
There is provided a clock transferring apparatus for synchronizing a pattern signal synchronized with a reference clock with a variable clock based on an oscillation source different from that of the reference clock, having a rate clock generating section for generating a rate clock whose number of pulses within a predetermined period is almost equal with a number of pulses of the variable clock within the predetermined period by thinning out the pulses within the reference clock, a pattern generating section for generating the pattern signal corresponding to the pulses of the rate clock and a FIFO memory that stores data of the pattern signal corresponding to the pulses of the rate clock and outputs the stored data corresponding to the pulses of the variable clock.

REFERENCES:
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patent: 2004/0143406 (2004-07-01), Nishikobara et al.
patent: 2004/0207436 (2004-10-01), Suda et al.
patent: 2004/0239310 (2004-12-01), Oshima et al.
patent: 2004/0252802 (2004-12-01), Yamaguchi
patent: 2005/0258856 (2005-11-01), Kishimoto et al.
patent: 2006/0031689 (2006-02-01), Yang et al.
patent: 3-219739 (1991-09-01), None
patent: 7-312591 (1995-11-01), None

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