Clock duty cycle based access timer combined with standard...

Details Clock duty cycle based access timer combined with standard... Clock duty cycle based access timer combined with standard...

2007-09-25

2007-09-25

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000, C714S744000

Reexamination Certificate

active

11057318

ABSTRACT:
An output of an element under test is captured and stored, through a multiplexer, in a capture register. At a clock edge (either rising or falling edge) the element under test catches the “edge” and “strobes” the output. The multiplexer is strobed, and the delay and duty cycle are measured. Both the rising and falling edge are used as the timer.

REFERENCES:
patent: 2003/0196150 (2003-10-01), Linam et al.
IBM, Integer Divisible Frequency Divider with Symmetric Outputs, May 1, 1996, IBM Technical Disclosure Bulletin, May 1996 vol. 39, pp. 187-188.
IBM, Test Bus Architecture, Aug. 1, 1989, IBM Technical Disclosure Bulletin, Aug. 1989, vol. 32, pp. 21-27.

Affiliated with

Also associated with

Rating

Clock duty cycle based access timer combined with standard... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock duty cycle based access timer combined with standard..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock duty cycle based access timer combined with standard... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3756398