Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-05-27
2008-05-27
Chung, Phung M. (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S736000, C714S718000
Reexamination Certificate
active
11054566
ABSTRACT:
A method and apparatus for implementing ABIST data compression and serialization for memory built-in self test of SRAM with redundancy. The method includes providing detection signals asserted for one failing data out, two failing data outs, and greater than two failing data outs. The method also includes individually encoding the failing bit position of each corresponding failing data out with a binary representation value corresponding therewith. The method further includes serializing results of the providing detection signals and the individually encoding, and transmitting results of the serializing to a redundancy support register function on a single fail buss.
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Dawson James W.
Knips Thomas J.
Plass Donald W.
Reyer Kenneth J.
Augspurger Lynn
Cantor & Colburn LLP
Chung Phung M.
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