Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-10-16
2007-10-16
Lamarre, Guy (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000
Reexamination Certificate
active
10709389
ABSTRACT:
Disclosed is an integrated circuit chip structure that has a chip level test access port (TAP) controller and a plurality of embedded TAPs connected to the chip level TAP. Because the embedded TAPs have lengths that differ from the chip level TAP IR, and the embedded TAP IR lengths may differ from each, the chip level TAP includes a flexible length instruction register architecture adapted to accommodate the different length instruction registers of the embedded TAPs while using a constant length chip level instruction register definition for all IR accesses through the chip level TAP. Further, the invention includes selection logic adapted to actively connect only a single embedded TAP to the chip level TAP at a time.
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Grupp Richard J.
Kunselman Gary L.
Oakland Steven F.
Gibb & Rahman, LLC
Lamarre Guy
LeStrange, Esq. Michael
Tabone, Jr. John J.
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