Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-09-11
2007-09-11
Lamarre, Guy (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000
Reexamination Certificate
active
11654291
ABSTRACT:
An AC boundary scan cell is disclosed. For one embodiment the AC boundary scan cell includes a first multiplexer, a second multiplexer, a first data shift register, a second data register, an XOR logic gate, and a third multiplexer. For one such embodiment the AC boundary scan cell includes an SDI line, an SDO line, a TDI line, a TDO line, a ShiftDR signal input line, an AC_Pattern_Clock or ClockDR signal input line, an UpdateDR signal input line, and a Mode signal input line. The AC boundary scan cell also includes an AC_Pattern_Source signal input line and an AC_Test signal input line. For one such embodiment, each line is coupled to receive the corresponding signal from the boundary scan logic.
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Baeg Sang Hyeon
Chung Sung Soo
Chaudry Mujtaba K.
Cisco Technology Inc.
Lamarre Guy
Thelen Reid Brown Raysman & Steiner LLP
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