Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-05-13
2008-05-13
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S727000, C714S744000, C714S030000, C327S261000, C327S269000, C327S270000, C713S400000, C713S401000
Reexamination Certificate
active
10908637
ABSTRACT:
A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated circuit. The scan chain is used to test the integrated circuit using a sequential scan technique (e.g., Automatic test pattern generation (ATPG)). Due to the programmability of delay magnitude, the burden on a designer to achieve synchronization of the data input with the clock signal while testing, is reduced.
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Acharya Yatin R
Bhat Anand
Trimmings John P
Tung Yingsheng
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