High speed vector access method from pattern memory for test...
High-performance IEEE1149.1-compliant boundary scan cell
High-resistance contact detection test mode
High-speed algorithmic pattern generator
High-speed level sensitive scan design test scheme with...
High-speed semiconductor memory test device
High-speed serial transfer device test method, program, and...
Host port interface
Hybrid algorithm for test point selection for scan-based BIST
Hybrid built-in self test (BIST) architecture for embedded...
Hybrid scan-based delay testing technique for compact and...
Hyperjtag system including debug probe, on-chip...