Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-12-25
2007-12-25
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000
Reexamination Certificate
active
10653959
ABSTRACT:
A scan-based method for testing delay faults in a circuit comprising controlling a subset of state inputs of the circuit by a skewed-load approach and controlling all inputs other than said subset of state inputs by a broad-side approach.
REFERENCES:
patent: 5357572 (1994-10-01), Bianco et al.
patent: 5675589 (1997-10-01), Yee
patent: 5774474 (1998-06-01), Narayanan et al.
patent: 2004/0177299 (2004-09-01), Wang et al.
D. Belete, A. Razdan, W. Schwarz, R. Raina, C. Hawkins, and J.Morehead. Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor. In Proceedings IEEE International Test Conference, pp. 1111-1119, 2002.
J. L. Carter, V. S. Iyengar, and B. K. Rosen. Efficient Test Coverage Determination for Delay Faults. In Proceedings IEEE International Test Conference, pp. 418-427, 1987.
J.-S. Chang and C.-S. Lin. Test Set Compaction for Combinational Circuits. In IEEE Trans. on Computer-Aided Design of Integrated Circuit and System, vol. 14(11):1370-1378, Nov. 1995.
S. Comen. DFT-focused chip testers: What can they really do? In Proceedings IEEE International Test Conference, p. 1120, 2000.
B. Dervisoglu and G. Stong. Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement. In Proceedings IEEE International Test Conference, pp. 365-374, 1991.
P. Goel. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits}. In IEEE Tranactions. on Computers, vol. C-30(3), Mar. 1981.
P. Goel and B.C. Rosales. Test Generation & Dynamic Compaction of Tests. In Dig. Papers Test Conference, pp. 182-192, 1979.
L. H. Goldstein and E. L. Thigpen. SCOAP: Sandia Controllability/Observability Analysis Program. In Proceedings IEEE-ACM Design Automation Conference, pp. 190-196; 1980.
K. Heragu, J. H. Patel, and V. D. Agrawal. SIGMA: A Simulator for Segment Delay Faults. In Proceedings IEEE International Conference on Computer-Aided Design, pp. 502-508, 1996.
A. K. Pramanick and S. M. Reddy. On the Fault Coverage of Gate Delay Fault Detecting Tests. IEEE Trans. on Computer-Aided Design of Integrated Circuit and System, vol. 16(1):78-94, Jan. 1997.
I. Pomeranz, L. N. Reddy, and S. M. Reddy. COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits. In Proceedings IEEE International Test Conference, pp. 194-203, 1991.
G. D. Robinson. DFT-focused chip testers: What can they really do? In Proceedings IEEE International Test Conference, pp. 1119, 2000.
J. Savir. Skewed-Load Transition Test: Part I, Calculus. In Proceedings IEEE International Test Conference, pp. 705-713, 1992.
J. Savir. Broad-side Delay Test. In IEEE Trans. on Computer-Aided Design of Integrated Circuit and System, vol. 13(8):1057-1064, Aug. 1994.
J. Savir and R. Berry. At-Speed Test is not Necessarily an AC Test. In Proceedings IEEE International Test Conference, pp. 722-728, 1991.
J. Saxena, K. M. Butler, J. Gatt, R. R, S. P. Kumar, S. Basu, D. J. Campbell, and J. Berech. Scan-Based Transition Fault Testing—Implementation and Low Cost Test Challenges. In Proceedings IEEE International Test Conference, pp. 1120-1129, 2002.
G. L. Smith. Model for Delay Faults Based Upon Paths. In Proceedings IEEE International Test Conference, pp. 342-349, 1985.
J. Savir and S. Patil. Scan-Based Transition Test. IEEE Trans. on Computer-Aided Design of Integrated Circuit and System, vol. 12(8), Aug. 1993.
J. Savir and S. Patil. Broad-Side Delay Test. IEEE Trans. on Computer-Aided Design of Integrated Circuit and System, vol. 13(8), Aug. 1994.
S. Wang and S. T. Chakradhar. A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs. To appear in Proceedings IEEE International Test Conference, 2003.
J. A. Waicukauski, E. Lindbloom, B. K. Rosen, and V. S. Iyengar. Transition Fault Simulation. IEEE Design & Test of Computers, pp. 32-38, Apr. 1987.
Chakradhar Srimat T.
Liu Xiao
Wang Seongmoon
Britt Cynthia
Gandhi Dipakkumar
NEC Laboratories America, Inc
Sughrue Mion Pllc.
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