High-speed level sensitive scan design test scheme with...

Details High-speed level sensitive scan design test scheme with... High-speed level sensitive scan design test scheme with...

2007-02-13

2007-02-13

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S744000

Reexamination Certificate

active

10908007

ABSTRACT:
This invention describes a method of synchronizing test clocks in an LSSD system to achieve near simultaneous arrival of the clock signals at the inputs of all LSSD registers. The method relies on pipelining the latches to distribute the test clocks, where all pipeline latches are synchronized by the system clock. This enhancement improves the frequency at which the test clocks switch and improve the testing throughput by reducing testing time, resulting in significant reductions in testing hardware and overall time required for system test, without compromising any of the benefits associated with conventional LSSD techniques. The method further enhances the distribution of the test clock signals to points throughout the entire chip, with a distribution network that is tailored according to a desired LBIST speed.

REFERENCES:
patent: 4893072 (1990-01-01), Matsumoto
patent: 6058496 (2000-05-01), Gillis et al.
patent: 6452435 (2002-09-01), Skergan et al.
patent: 6539491 (2003-03-01), Skergan et al.
patent: 6567943 (2003-05-01), Barnhart et al.
patent: 2002/0073380 (2002-06-01), Cooke et al.
patent: 2002/0166098 (2002-11-01), Chang et al.

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