Hybrid built-in self test (BIST) architecture for embedded...

Details Hybrid built-in self test (BIST) architecture for embedded... Hybrid built-in self test (BIST) architecture for embedded...

2008-03-28

2009-12-08

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S744000, C714S718000

Reexamination Certificate

active

07631236

ABSTRACT:
Disclosed are embodiments of a built-in self-test (BIST) architecture that incorporates a standalone controller that operates at a lower frequency to remotely perform test functions common to a plurality of embedded memory arrays. The architecture also incorporates command multipliers that are associated with the embedded memory arrays and that selectively operate in one of two different modes: a normal mode or a bypass mode. In the normal mode, instructions from the controller are multiplied so that memory array-specific test functions can be performed locally at the higher operating frequency of each specific memory array. Whereas, in the bypass mode, multiplication of the instructions is suspended so that memory array-specific test functions can be performed locally at the lower operating frequency of the controller. The ability to vary the frequency at which test functions are performed locally, allows for more test pattern flexibility.

REFERENCES:
patent: 5614838 (1997-03-01), Jaber et al.
patent: 5689466 (1997-11-01), Qureshi
patent: 5754758 (1998-05-01), Baeg et al.
patent: 5796745 (1998-08-01), Adams et al.
patent: 5805611 (1998-09-01), McClure
patent: 5822228 (1998-10-01), Irrinki et al.
patent: 5930814 (1999-07-01), Lepejian et al.
patent: 5961634 (1999-10-01), Tran
patent: 6055658 (2000-04-01), Jaber et al.
patent: 6085346 (2000-07-01), Lepejian et al.
patent: 6343366 (2002-01-01), Okitaka
patent: 6509766 (2003-01-01), Pomichter et al.
patent: 6510530 (2003-01-01), Wu et al.
patent: 6550033 (2003-04-01), Dwork
patent: 6779144 (2004-08-01), Hayashi et al.
patent: 6978402 (2005-12-01), Hirabayashi
patent: 6993696 (2006-01-01), Tanizaki et al.
patent: 7437636 (2008-10-01), Rajski et al.
patent: 2002/0059543 (2002-05-01), Cheng et al.
patent: 2002/0170003 (2002-11-01), Hirabayashi
patent: 2002/0171447 (2002-11-01), Ernst et al.
patent: 2003/0034791 (2003-02-01), Huang et al.
patent: 2004/0085082 (2004-05-01), Townley
patent: 2005/0120270 (2005-06-01), Anand et al.
patent: 2005/0193253 (2005-09-01), Fales et al.
patent: 100 60 436 (2000-05-01), None
Dear, et al., “Test Strategy Planning Using Economic Analysis,” Journal of Electronic Testing, vol. 5, 1994, pp. 137-155.
Powell, et al., “BIST for Deep Submicron ASIC Memories with High Performance Application,” Proceedings IEEE int. Test Conf., 2003, pp. 386-393.
Gorman, et al., “Low Cost Test of High Bandwidth Embedded Memories,” Proceedings IEEE Custom Integrated Circuits Conf., 2006, pp. 445-448.
Dreibelbis, et al., “Processor Based Built-in Self Test for Embedded DRAM,” IEEE Journal of Solid State Circuits, vol. 33, No. 11, 1998, pp. 1731-1740.
Horowitz, et al., “Low-Power Digital Design,” Proceedings IEEE Symp. on Low Power Electronics, 1994, pp. 8-11.
Kirihata, et al., “An 800-MHz Embedded DRAM with a Concurrent Refresh Mode,” IEEE Journal of Solid State Circuits, vol. 40, No. 6, 2005, pp. 1377-1387.
Huang, et al., “A High-Speed Built-In-Self-Test for DRAMs,” Proceedings Int. Symp. On VLSI Technology Systems and Applications, 1999, pp. 50-53.

Affiliated with

Also associated with

Rating

Hybrid built-in self test (BIST) architecture for embedded... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hybrid built-in self test (BIST) architecture for embedded..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hybrid built-in self test (BIST) architecture for embedded... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4132548