Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-06-15
2001-07-03
Hua, Ly V. (Department: 2131)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000
Reexamination Certificate
active
06256759
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a hybrid cost reduction technique for test point selection for scan-based built-in self-testing (BIST) of a sequential circuit.
2. Description of the Related Art
Integrated circuits (IC) are tested to ensure that the component is defect-free after being manufactured and/or remains in proper working condition during use. Testing of the IC may be accomplished by applying a test pattern to stimulate the inputs of a circuit and monitoring the output response to detect the occurrence of faults. The test patterns may be applied to the circuit using an external testing device. Alternatively, the pattern generator may be a BIST structure comprising part of the internal circuitry in the IC which generates the test patterns.
Although it is desirable when testing the logic circuit to use exhaustive testing by checking the circuit output response to all 2
n
possible input permutations, this approach becomes impracticable as the number of input variables n increases. Thus, a related technique, referred to as pseudo-random testing, is employed when the number of input variables is so large that it becomes impracticable to use an exhaustive testing approach. Pseudo-random testing is an alternative technique that generates test patterns in a random fashion from the 2
n
possible patterns. In this approach fewer than all of the 2
n
patterns are tested. Because of the relatively low hardware overhead and the simplicity of test pattern generation, pseudo-random testing is a preferred technique for BIST. Practical circuits, however, often contain random pattern resistant faults which result in unacceptable low fault coverages for a reasonable test length. Under these circumstances the testability of the circuit may be improved by inserting test points into the circuit.
A conventional scan-based BIST structure is shown in FIG.
1
and disclosed in U.S. Pat. No. 5,329,533, which is herein incorporated by reference. In order to test a sequential circuit it must first be converted to either a full or partial-scan circuit. This conversion may be realized by replacing some or all of the flip-flops in the circuit under test with scan flip-flops and connecting the scan flip-flops into one or more scan chains. If all of the flip-flops are replaced, then the circuit under test is a full scan circuit and the network N is a combinational circuit. In a partial scan BIST scheme, only crucial flip-flops selected using a cycle-breaking algorithm, as for example described by Cheng and Agrawal, “A Partial Scan Method for Sequential Circuits with Feedback,”
IEEE Transactions on Computers,
vol. 39, no. 4, pp. 544-548, April 1989, which is herein incorporated by reference, are replaced with scan flip flops and the network N is a near acyclic circuit (NAC), that is, a synchronous sequential circuit whose corresponding directed graph G does not contain any cycle with length greater than one.
As shown in
FIG. 1
, the scan-based BIST structure includes a test pattern generator
100
which supplies random patterns to primary inputs and, via scan chains, to pseudo-inputs (outputs of the scan flip-flops). The test pattern generator
100
includes a linear feedback shift register (LFSR)
110
and a phase shifter (PS)
120
. Data from the primary outputs and, via the scan chain, from pseudo-outputs (inputs of the scan flip-flops) are compacted by an output data compactor (ODC)
130
such as a multiple input signature register (MISR)
140
and a space compactor (SC)
150
.
To begin testing, the integrated circuit is placed in a test mode during which the bits of a test vector are scanned into the chain of scan flip-flops of the integrated circuit. After the test data is entered, the integrated circuit is returned to a non-test mode during which the scan flip-flops respond to the previously received test data in their usual manner. A predetermined period of time later, the test mode is reentered and the output response to the scan flip-flops is captured.
One or more test points, e.g. control points and/or observation points, may be inserted into the circuit under test to improve the fault coverage. An observation point is inserted at a node to improve the observabilities of the node and all other nodes that directly/indirectly feed the node. The effect of inserting an observation point on the circuit under test
160
is represented by the hatched region in
FIG. 2
a.
FIGS. 2
b
and
2
c
illustrate the circuit before and after insertion of the observation point. As is clearly evident from a comparison of
FIGS. 2
b
and
2
c,
an observation point is implemented by connecting the node to the ODC.
A control point may be inserted at a node to improve controllabilities as well as observabilites of nodes in a circuit. Changing the controllability of a node inherently also changes the controllabilities of nodes influenced by the node as indicated by the shaded region in
FIG. 3
a.
In addition, the observabilites of nodes in the hatched area of
FIG. 3
a,
which includes the shaded region, are altered.
FIGS. 3
b
and
3
c
illustrate the circuit before and after insertion of a control point. The added gate G in
FIG. 3
c
is either an OR gate (1-control point) or an AND gate (0-control point). Signal t is connected to a random source whose 1-controllability (defined as the probability of having a logic value “1”) is 0.5 at the BIST mode. During the normal mode, 1-controllability of signal t is 0 for a 1-control point and 1 for a 0-control point. If the 1-controllability of s is too small, an OR gate is inserted such that during the BIST mode the 1-controllability s′ is higher than 0.5. On the other hand, if the 1-controllability of s is too large, an AND gate is added such that the 1-controllability of s′ is smaller than 0.5. Regardless of which gate is added, the observabilities of all the nodes that affect s are reduced and, in the worst case is reduced by approximately one half.
Fault simulation is one method of selecting test points by identifying the reconvergent fanout points and gates which block the activation and propagation of faults. These points and gates are classified as good test point candidates. However, fault simulation is costly If in terms of computational complexity and hence, is not practical for relatively large circuits.
An alternative approach is to use testability measures to select test points, as for example controllability/observability programs (COP), as described by F. Brglez, “On Testability of Combinational Networks,”
Proc. of International Symposium on Circuits and Systems,
pp. 221-225, May 1984, which is herein incorporated by reference. COP is a well known procedure to estimate the 1-controllability C
s
and observability O
s
of every signal s in a combinational network. The variable C
s
represents the probability that node s has a logic value “1”; whereas O
s
represents the probability that the logic value at node s can be observed via at least one of the primary outputs. The variables C
s
and O
s
are calculated by sweeping the circuit once. Controllabilities and observabilities themselves are not sufficient to determine the selection of test points, however, because they represent a local testability impact rather than a global testability impact due to the insertion of a test point.
R. Lisanke et al., “Testability-Driven Random Test Pattern Generation,”
IEEE Tran. on computer
-
Aided Design,
vol. CAD-6, pp. 1082-1087, November 1987, which is herein incorporated by reference, defines a cost function U that is used to estimate the global circuit testability
U
=
1
&LeftBracketingBar;
F
&RightBracketingBar;
(
∑
i
∈
F
1
Pd
i
)
(
1
)
where F is the fault set;
|F| is the cardinality of F; and
Pd
i
is the detection probability of fault i.
For the stuck-at-fault model, Pd
i
may be expressed as one of the following two equations:
Pd
s/0
=C
s
·O
s
, for stuck-at-0 fault at s
Pd
s/1
=(1−
C
s
)·0
s
, for stuck-at-1 fault at s
In the c
Bhawmik Sudipta
Cheng Kwang-Ting
Lin Chih-Jen
Tsai Huan-Chih
Agere Systems Inc.
Hua Ly V.
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