Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2009-01-05
2009-11-03
Tu, Christine T (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07613966
ABSTRACT:
A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission path between the probe and the on-chip instrumentation. The on-chip instrumentation includes an on-chip instrumentation concentrator and an on-chip instrumentation de-concentrator. The probe includes a probe concentrator and a probe de-concentrator. The probe concentrator concentrates signals from the test instruments into a first serial signal stream for transmission over the connector mechanism. The on-chip instrumentation de-concentrator de-concentrates the first serial signal stream into signals to be directed to at least one of the processor cores. The on-chip instrumentation concentrator concentrates signals from the processor cores into a second serial signal stream for transmission over the connector mechanism. The probe de-concentrator de-concentrates the second serial signal stream into signals to be directed to at least one of the testing instruments. Using this system, the testing instruments are able to simultaneously access and control respective processor cores. In one preferred embodiment the plurality of signals are directed to the processor cores using a plurality of loops, each loop having a chain of nodes, each of the processor cores connected to a respective node.
REFERENCES:
patent: 5712858 (1998-01-01), Godiwala et al.
patent: 5875293 (1999-02-01), Bell et al.
patent: 6272137 (2001-08-01), Noiri
patent: 6460171 (2002-10-01), Couvert et al.
patent: 6560734 (2003-05-01), Whetsel
patent: 6584590 (2003-06-01), Bean
patent: 6643810 (2003-11-01), Whetsel
patent: 6678645 (2004-01-01), Rajsuman et al.
patent: 6785854 (2004-08-01), Jaramillo et al.
patent: 6944132 (2005-09-01), Aono et al.
patent: 7100086 (2006-08-01), Kudo et al.
Collins, Robert R., “In-Circuit Emulation—A Powerful Hardware Tool for Software Debugging”, http://www.rcollins.org/ddj/Jul97/, 5 pages, copyright 1991-1999.
Dada, Gerardo A., “Reducing Time to Market: Parallel Software Development with Emulation and Simulation Tools for MXC Architectures”, Motorola, Digital dna, White Paper, Motorola, Inc. 16 pages (2004).
Leatherman, Rick et al., “Processor and System Bus on Chip Instrumentation”, at 14 pages, at least as early as Dec. 29, 2004.
Stollon, Neal et al., “Multi-Core Embedded Debug for Structured ASIC Systems”, DesignCon 2004, http://www.designcon.com/conference/2004/2-TA3.pdf, 23 pages (2004).
Stollon, Neal et al., “A Reconfigurable Bus IP for Modular Function Integration”, ACM, 6 pages, copyright 2000.
Veal, Robert L. et al., “Multi-Core SoC Platform Integration Using AMBA”, DesignCon 2002 System on Chip and IP Design Conference, Infinite Technology Corporation, 18 pages (2002).
Vermeulen, Bart et al., “Test and Debug Strategy of the PNX8525 Nexperia Digital Video Platform System Chip”, ITC International Test Conference, IEEE, pp. 121-130 (2001).
Wilson, Ron, “PalmChip Bus Patent Threatens Most SoCs”, http://www.eetimes.com/story/OEG20030801S0043, 4 pages, Aug. 4, 2003.
Ableidinger Bruce J.
Edgar Ernest Lewis
Cooley Godward Kronish LLP
MIPS Technologies Inc.
Tu Christine T
LandOfFree
Hyperjtag system including debug probe, on-chip... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hyperjtag system including debug probe, on-chip..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hyperjtag system including debug probe, on-chip... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4112812