High-speed algorithmic pattern generator

Details High-speed algorithmic pattern generator High-speed algorithmic pattern generator

2000-10-31

2004-12-28

Torres, Joseph D. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S715000

Reexamination Certificate

active

06836868

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to an algorithmic a pattern generator for generating a vector sequence, and in particular to a high-speed algorithmic pattern employing separate vector and instruction memories.
2. Description of Related Art
A typical pattern generator (or vector generator) produces an output pattern data word (a “vector”) on each pulse of a reference clock signal. Pattern generators are often employed in integrated circuit testers to produce vector sequences for controlling the behavior of the testers.
FIG. 1
illustrates a typical prior art integrated circuit (IC) tester
10
including a set of N tester channels CH(
0
)-CH(N), each linked to a separate terminal of an integrated circuit device under test (DUT)
12
. A test is organized into a succession of test cycles, and during each test cycle each channel CH(
0
)-CH(N) may transmit a test signal to a DUT terminal or sample a DUT output signal produced at that terminal to determine whether the DUT is behaving as expected. During the test, a central clock generator
14
supplies a master clock signal MCLK to all tester channels CH(
0
)-CH(N), and all channels synchronize their test activities to that master clock signal.
Tester channel CH(
0
), typical of the other tester channels, includes a pattern generator
16
programmed by a central host computer
18
to produce a vector prior to the start of each test cycle. A timing signal generator
20
supplies a “period” clock signal PCLK (derived from the MCLK signal) to pattern generator
16
marking the start of each test cycle telling the pattern generator when to generate a next vector. Each vector output of pattern generator
16
references a test activity that channel CH(
0
) is to carry out during the test cycle, such as changing the state of a test signal or sampling a DUT output signal. The vector may also reference a particular time during the test cycle at which the test activity is to occur. When the channel is to sample a DUT output signal, the vector will also indicate an expected state of the DUT output signal. The bit width of the vector limits the number of different combinations of test activities and timings that the vector is able to reference.
A formatter circuit
22
receives and decodes each vector to supply a set of control signals to a pin electronics circuit
24
for generating the test input to DUT
12
and samples DUT output signals. State changes in those control signals tell pin electronics circuit
24
how and when to change test signal states or when to sample the DUT output signal. The vector input from pattern generator
16
at the start of a test cycle tells formatter
22
when and how to change the states of the control signals supplied to pin electronics circuit
24
, and formatter produces those control signal state changes using as timing references a set of timing signals TS supplied by timing signal generator
20
. When pin electronics circuit
24
samples a DUT output signal, it determines the output signal's logic state, and transmits a signal back to formatter
22
indicating that logic state. Formatter
22
then compares the DUT output signal's logic state to an expected state referenced by the input vector for the current test cycle. When the expected and actual DUT output signal states fail to match, formatter
22
generates a FAIL signal and sends it back to host computer
18
to indicate that the DUT has failed the test.
FIG. 2
illustrates a simple prior art pattern generator
16
A that has been used in the past to implement pattern generator
16
of FIG.
1
. Before the start of a test, host computer
18
of
FIG. 1
writes the vectors needed for all test cycles into consecutive addresses of a random access memory
30
. During the test, a counter
32
clocked by the period clock signal PCLK increments its output count at the start of each test cycle. The output count read addresses memory
30
and the PCLK read enables memory
30
so that it reads out a next vector at the start of the next test cycle. While this pattern generator architecture is suitable for short IC tests spanning relatively few test cycles, such a pattern generator requires an impractically large memory
30
to store all of the vectors needed for long tests spanning a large number of test cycles.
FIG. 3
illustrates a prior art “algorithmic” pattern generator
16
B that also has been used to implement pattern generator
16
of FIG.
1
. Pattern generator
16
B includes a programmable counter
37
for supplying a sequence of addresses to a memory
34
that not only stores a vector at each address but also stores an instruction with the vector at each address. Thus whenever memory
34
reads out a vector for a particular test cycle, it also reads out an instruction. That instruction tells an instruction processor
36
how to tell counter
37
to generate the memory address of the vector for the next test cycle. In response to various instructions, instruction processor
36
can signal counter
37
to increment its current output address, to keep its output address unchanged, or to load a new address provided by the instruction processor. Instruction processor
36
can, for example, perform repeats, loops and subroutine calls. Since many tests involve highly repetitive activities at the DUT pin, a properly designed instruction set can define a large repetitive vector sequence using much less space in memory
34
to store the instructions than would be required to directly store the vector sequence in memory
30
of pattern generator
16
A FIG.
2
.
However the inherent address/instruction feedback loop delay of pattern generator
16
B limits its operating frequency. The test cycle period can be no shorter than the total time required for an address to travel from counter
37
to memory
34
, for memory
34
to read out the vector and instruction at that address, for the instruction to travel back to instruction processor
36
, and for instruction processor
36
to process that instruction and signal counter
37
to generate the address for the next cycle, and for counter
37
to update its output address. A major portion of the feedback delay occurs in memory
34
, typically a dynamic random access memory (DRAM). A DRAM has a relatively long inherent delay between receiving an input address and reading out a data word stored at that address. In some applications a DRAM's delay can be overcome by implementing memory
44
with a DRAM such as a Fujitsu Model “FCRAM” that can operate in a pipeline fashion; even though it may take for example 5 read cycles after receiving an input address to read out data at that address, such DRAM can accept addresses and read out stored vectors once every read cycle. Alternatively memory
44
can be implemented by interleaved banks of DRAMs that are alternately read accessed. However in pattern generator
16
B, where the instruction read out of memory
34
controls the next address to be supplied to memory
34
, the pattern generator cannot take advantage of the pipeline capability of memory
34
.
We could increase the frequency of operation of the pattern generator
16
B of
FIG. 3
by implementing memory
34
and instruction processor
36
on the same IC and by using a faster kind of memory, such as an SRAM, to implement memory
34
, thereby shortening the feedback delay. However placing memory
34
on the same IC as processor
36
and counter
37
and using a fast SRAM to implement memory
34
is not practical or economical for general purpose testers requiring a very large memory
34
to hold all the instructions and vectors needed for a test.
FIG. 4
illustrates a prior art pattern generator
16
C providing a fast cache memory
38
on the same IC
40
as an instruction processor
42
. (See for example U.S. Pat. No. 6,009,540 issued Dec. 28, 1999 to Kuglin et al, incorporated herein by reference.) All of the test instructions and vectors are stored in a large external DRAM memory
44
, similar to memory
34
of FIG.
3
. During a test,

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