LandOfFree - US Patents - Listing for Error detection/correction and fault detection/recovery,Pulse or data error handling,Digital logic testing

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Driver for integrated circuit chip tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Driver IC and inspection method for driver IC and output device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Dual controllers for scan paths, distributors, and collectors

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Dual mode memory for IC terminals

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Dual mode memory for IC terminals

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Patent

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Dual mode test access port method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Dual scan chain design method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Dual site loadboard tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Patent

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Duty cycle characterization and adjustment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Duty cycle characterization and adjustment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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DVI link with parallel test data

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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DVI link with parallel test data

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Dynamic logic element having non-invasive scan chain insertion

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Patent

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Dynamic logic scan gate method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Dynamic scan chains and test pattern generation...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Dynamic scan circuitry for A-phase

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Dynamic verification traversal strategies

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Dynamically reconfigurable precision signal delay test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Dynamically reconfigurable precision signal delay test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

[ 0.00 ] – not rated yet Voters 0 Comments 0

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