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Apparatus and method for generating addresses in a built-in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Apparatus and method for generating addresses in a SRAM built-in

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Apparatus and method for hardware-assisted diagnosis of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for high speed sampling or testing of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for high-speed SAS link protocol testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for high-speed SAS link protocol testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for hybrid pin control of boundary scan app

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Apparatus and method for initializing an integrated circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for initializing an integrated circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for interfacing a high speed scan-path...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for interfacing boundary-scan circuitry...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for isolating portions of a scan path...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for multi-cycle memory access mapped to...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for parallel testing of multiple...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for performing a multi-value polling...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for progammable parametric toggle...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for programmable built-in self-test and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for programmable fuse repair to support...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for programmable fuse repair to support...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for providing a diagnostic problem...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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