Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-01-20
2008-10-14
Kerveros, James C. (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S710000
Reexamination Certificate
active
07437637
ABSTRACT:
An apparatus and method for allowing for dynamic wordline repair in a clock running system in addition to allowing for programmable fuse support of combined Array Built-In Self-Test (ABIST) and Logic Built-In Self-Test (LBIST) testing. The method makes use of programmable fuses which contain Level Sensitive Scan Design (LSSD) latches which also have a system port. The system port allows for simpler reading of the fuses as well as for the dynamic updates of the programmable fuses for wordline and other repairs.
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patent: 4768193 (1988-08-01), Takemae
patent: 6182257 (2001-01-01), Gillingham
patent: 6505305 (2003-01-01), Olarig
patent: 6651202 (2003-11-01), Phan
patent: 6973605 (2005-12-01), Templeton et al.
McNamara Timothy G.
Meaney Patrick J.
Mechtly Bryan L.
Augspurger Lynn L.
International Business Machines - Corporation
Kerveros James C.
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