Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-06-29
2004-06-29
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06757856
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to testing and diagnosing semiconductor devices, and more specifically, the invention relates to the testing and diagnosing of shift registers.
2. Prior Art
Structural testing and defect-diagnosis of semiconductor logic devices depend significantly on the minimum functionality of the underlying design-for-test structures embedded in the logical design of such devices. Scan-based methods of structural logic testing—of which Level-Sensitive Scan Design (LSSD) is but one example—configure all the state—elements (flip-flops or latches) into one or more serial shift-registers (often referred to as scan-chains or scan-strings) so that the values in these state-elements may be directly set or interrogated by operation of the shift-registers.
Conventional defect-diagnosis of failing logic tests normally proceeds on the assumption that the shift-registers have been determined to be a-priori functional (since the actual test-input stimulus being applied to the device during the failing tests cannot otherwise be assumed to be fully known). This functionality is assured by preceding the application of all such scan-based logic tests with functional-verification tests of the shift-registers. In LSSD, these are called the flush and scan tests. They verify the logical continuity of each serial-shift-register scan-path, and establish that each state-element in each shift-register can set and hold both logical-zero and logical-one values
When either the flush or scan tests fail, the basic design-for-test infrastructure is broken—and none of the succeeding scan-based logic tests can be applied without expectation of massive fails, since the intended test stimulus/response will be corrupted by the broken shift-register(s). Moreover, localization and detailed diagnosis of a defect in a broken shift-register can be a very difficult problem, especially as the shift-register bit-length increases.
Broken-shift-register problems are most prevalent early in a technology-life-cycle, when device-yields tend to be the lowest, and when pressure for rapid yield-learning and volume ramp-up is the highest. The conventional approach (in microprocessor design) to managing this exposure has been to implement scan-design with as many separate shift-registers (64-80 or more) as the functional input/output (I/O) architecture of the device-design allows, thus permitting each shift-register to be of the shortest possible bit-length. Since microprocessors (and other standard products) typically utilize custom, device-specific test-fixturing, this high-pin-count approach to managing the risk of broken shift-registers has been an acceptable method.
In contrast, Application-Specific Integrated Circuit (ASIC) products have a long history of utilizing standardized, reusable test-fixturing to reduce overall test/fixturing costs across a large number of lower-volume device-designs sharing the same die configuration (chip image) and/or the same module package. This approach to multiple-device-design test standardization, often referred to as reduced-pin-count testing (RPCT), requires that each device-design implement an on-product boundary-scan structure to enable full scan-testing of all device-circuitry (except the I/O circuits) through a fixed-size signal-I/O interface comprising a maximum of 64 signal-I/Os contacted by full-function tester-channels for both wafer and module device-testing.
These 64 signal-I/Os must include all device-inputs required for test-clocking and control, as well as all scan-data-inputs and scan-data-outputs of the shift-registers. The 64-pin limit constrains most ASIC products to a practical upper-bound of approximately 24 shift-registers per device. Thus, a typical ASIC may have far-fewer, much-longer shift-registers than a microprocessor (or other standard product) of similar logical complexity. As ASICs become earlier adopters of leading-edge technology, their risk of broken-shift-register diagnostic problems is amplified by this difference in device-design style.
SUMMARY OF THE INVENTION
An object of this invention is to improve apparatus and method for diagnosing shift registers
Another object of the present invention is to more easily localize the position of a shift-register break.
A further object of this invention is to provide a method and apparatus for diagnosing shift registers that logically emulates the effect of having many more, shorter shift registers, while still maintaining the reduced pin-count interface that is so important to ASIC test economics.
These and other objectives are attained, in accordance with the present invention, by providing a systematic means of switching contiguous segments of each production-test shift-register into several diagnostic scan-configurations. If the functional scan-verification tests fail for the production-test scan-configuration, then these same verification tests can be repeated for the alternative, diagnostic scan configurations. Using the principle of superposition, the passing and failing LSSD flush/scan tests for these diagnostic configurations will allow the failing location to be localized to a single segment of the original failing shift-register.
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International Business Machines - Corporation
Scully Scott Murphy & Presser
Tu Christine T.
Walsh Robert A.
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