Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-06-11
2001-04-17
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S724000, C326S086000
Reexamination Certificate
active
06219812
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to digital circuits, and more particularly to circuits to interface DTL logic outputs to standard boundary-scan registers.
BACKGROUND OF THE INVENTION
The testing of integrated circuits commonly involves an operation of shifting test instructions and associated test data into an integrated circuit and subsequently analyzing the output generated by the integrated circuit. The Joint Test Access Group (JTAG) developed an integrated circuit and circuit board testing standard called the IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Std 1149.1-1990 and IEEE Std 1149.1a-1993 (referred to herein as the IEEE 1149.1 standard), which is incorporated herein by reference.
The IEEE 1149.1 standard defines test logic that can be included in integrated circuits to provide standardized approaches to testing an integrated circuit, testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board, and observing or modifying circuit activity during the circuit's normal operation.
Many complex circuits use boundary-scan testing techniques to test the output buffers of the circuit. For circuits using conventional two-state or three-state CMOS output buffers, designers commonly use the boundary-scan implementation defined in the IEEE 1149.1 standard. As is well known, a boundary-scan implementation allows for testing of interconnects in a board environment by loading or “scanning in” test patterns into a series of interconnected boundary-scan registers (BSRs). Each test pattern loaded in the BSRs provides a different set of control and data signals to the output drivers. The response of the output drivers to the test patterns can be captured by an adjacent circuit on the board and scanned out. To run a functional test vector, an input test pattern is scanned in through the BSRs. After one or more clock cycles, the response of the circuit can then be captured in the BSRs and either scanned out or monitored at the output pads.
FIG. 1
is a circuit diagram of a portion of a circuit
100
using a conventional boundary-scan implementation for I/O drivers that have three-state drivers (TSDs). The circuit
100
includes a conventional TSD
103
serving as an output driver, having an output lead connected to an I/O pad
104
. The circuit
100
includes conventional BSRs
102
and
112
, which are interconnected to form part of a “scan chain” for loading test patterns and scanning out capture data. BSR
102
has an input lead coupled to the output of flip-flop
101
. Flip-flop
101
provides an output enable, oe, signal to BSR
102
. An input of BSR
112
is coupled to the output of flip-flop
111
. Flip-flop
111
provides a data signal, d, input to BSR
112
.
In operation in the boundary-scan mode, BSRs
102
and
112
are loaded with a value for enabling or disabling TSD
103
, as desired. Accordingly, TSD
103
is controlled as desired by the test pattern loaded into the BSRs to test one of the various functions of the I/O driver. The output signal provided by TSD
103
can then be monitored at the I/O pad
104
and compared to an expected result.
Some high performance circuits such as, for example, microprocessors, use other types of drivers for improved performance. One type of driver that can be used is a linearized impedance control type (LIC) driver. A boundary-scan interfacing method for LIC drivers is disclosed in the commonly assigned patent application entitled “Method for Interfacing Boundary-Scan Circuitry With Linearized Impedance Control Type Output Drivers,” Ser. No. 08/885,054, which is herein incorporated by reference. A boundary-scan interface apparatus LIC drivers is disclosed in the commonly assigned patent application entitled “Boundary-Scan Circuit for Use With Linearized Impedance Control Type Output Drivers,” Ser. No. 08/885,012, which is herein incorporated by reference. Another type of driver that can be used is a Dynamic Termination Logic (DTL) type I/O driver. In DTL signaling systems, on-chip drivers act as receiver-end (i.e. parallel) terminators. This differs from previous parallel-terminated systems which generally use off-chip resistors for termination. In a driving mode, the DTL driver acts as a resistance controlled inverting output buffer. In a receiving mode, the DTL driver may (depending on its position within the system) remain active as a static terminating resistor, or it may be tri-stated. DTL driver control signals are not equivalent to the data and oe signals of a conventional CMOS TSD. Thus circuits using boundary-scan implementations according to the IEEE 1149.1 standard cannot be used with circuits having DTL drivers. Because the IEEE 1149.1 standard is widely used in the industry, there is a need for a system that allows DTL drivers to be used with boundary-scan implementations according to the IEEE 1149.1 specification.
SUMMARY OF THE INVENTION
The present invention provides a system for coupling a DTL driver to a boundary-scan implementation. In one embodiment adapted for the IEEE 1149.1 boundary-scan standard, the system converts data and output enable signals of the IEEE 1149.1 specification to q_up, q_dn, and q
25_
dn DTL control signals. In a further refinement, the system also converts functional q_up, q_dn and q
25_
dn signals provided by the circuit under test to the data and output enable signals of the IEEE 1149.1 specification. This feature is advantageously used to capture data into the BSRs of the IEEE 1149.1 boundary-scan implementation. As a result, the system allows the widely used IEEE 1149.1 boundary-scan standard to be used with DTL drivers.
In a particular implementation of the above embodiment, the system includes a first logic circuit for converting the functional q_up, q_dn and q
25_
dn signals (i.e., generated by the circuit under test) into “response” output enable and data signals to be captured in the Boundary-Scan Registers (BSRs). The system also includes a second logic circuit for converting the output enable and data signals from the BSRs into q_up, q_dn and q
25_dn signals. The first and second logic circuits of the system thereby allow the IEEE
1149.1 boundary-scan standard to be used with DTL drivers in a manner that is transparent to boundary-scan testers.
The second logic circuit can further include logic control signals to enhance system performance. A first logic control signal input to the second logic circuit determines which of two pull-down resistance values is used by the DTL driver when it is at a low logic level. A second logic control signal input to the second logic circuit determines whether the DTL driver in a receiving mode acts as a terminator or is in a high impedance state. A third logic control signal input to the second logic circuit places the DTL driver into a high impedance mode independent of the boundary-scan signals provided by the BSRs.
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De'cady Albert
Lin Samuel
Pennie & Edmonds LLP
Sun Microsystems Inc.
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