Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-04-28
2000-11-14
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714730, 714743, G01R 3128
Patent
active
061484261
ABSTRACT:
A memory address generator having a small chip area, a method for generating a memory address and a SRAM built-in self test (BIST) circuit using the same are described. When the number of addresses of a memory to be tested is 2.sup.n, where n is the number of bits in an address, the address generator includes an up counter for generating a first address of a series of sequentially increasing addresses, and an inverter for inverting the first address to generate a second address of a series of sequentially decreasing addresses. The address generator also includes a selector for selecting one of the first and second addresses, in response to a control signal, to output the selected address as an address of the memory. When the number of addresses of the memory to be tested is not 2.sup.n, the address generator includes an up counter for generating a first address of a series of sequentially increasing addresses up to a maximum address of the memory and a subtracter for subtracting the first address from the maximum address to generate a second address of a series of sequentially decreasing addresses. The address generator also includes a selector for selecting one of the first and second addresses, in response to control signal, to output the selected address as an address of the memory.
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Jun Hong-shin
Kim Heon-Cheol
Nguyen Hoa T.
Samsung Electronics Co,. Ltd
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