Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-08-31
2004-08-17
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000
Reexamination Certificate
active
06779142
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a system and method for testing electronic devices for operability. More particularly, the present invention relates to a system for performing testing of integrated circuits at full clock speed, using test equipment that operates at a speed slower than the full clock speed of the circuitry being tested.
2. Background of the Invention
The development of integrated circuits has become increasingly complex, due in large part to the ever increasing functionality offered by newly developed circuitry. Integrated circuits are constantly surpassing milestones in development, as more and more finctionality is packaged into smaller sizes. This enhanced functionality and the greater number of transistors packaged in an integrated circuit requires more rigorous testing requirements to insure reliability once the device is commercialized. Thus, new integrated circuit designs are repeatedly tested and debugged during the development process to minimize the number and severity of errors that may subsequently arise. Regardless of the rigor of the developmental testing, invariably a certain percentage of manufactured devices will fail prematurely. To prevent such devices from being sold or used in systems, typically some level of testing is performed on manufactured chips to identify those that may fail prematurely.
A number of different types of testing have been used to minimize the possibility of premature failure of manufactured chips. One of the more popular types of testing is Scan testing. Scan testing is a well recognized design-for-test (“DFT”) technique used for addressing certain testing problems in very large scale integrated (“VLSI”) circuits. See Eichelberger, et al., “A Logic Design Structure for LSI Testability,” (IEEE 1977). A full scan design technique transforms a given sequential circuit into a combinational circuit and shift register (referred to as a scan register) for the purpose of testing. This transformation makes it possible to obtain almost complete fault coverage using an Automatic Test Pattern Generation (“ATPG”) program. Typically, as part of the Scan test, large circuits are partitioned into smaller combinational circuits to facilitate fault isolation and failure analysis.
The scan design technique implements all or most of the state elements in the device under test, such as flip-flops and latches, as scannable flip-flops, which often are referred to as scan-flops. As shown in
FIG. 1
, a scan-flop
15
simply comprises a standard flip-flop
10
(that forms part of the circuit being tested) and an additional multiplexer
12
used for scan testing. Two inputs are provided to the multiplexer
12
, a D (data) input, and an SI (serial input). The multiplexer selects the D or SI input to pass to the flip-flop
10
, based on the status of the SHIFT (or ScanShift) signal. Thus, for example, if the ScanShift signal is asserted, the SI input passes to the D input of flip-flop
10
, producing a Q output signal and SO (Serial Out) output signal. Conversely, if ScanShift is de-asserted, the D input passes to the D input of flip-flop
10
, producing the Q output signal and the Serial Out signal. The flip-flop
10
is clocked by a clock signal (“CLK”). The use of the SI, SO and ScanShift signal permits the test equipment to perform tests on the flip-flop
10
and other circuitry connected to the flip-flop, such as other combinational logic.
An example of a device level scan register, or scan-path, appears in FIG.
2
. The scan-path includes a plurality of scan-flops
15
cascaded or chained together, all of which receive a CLK signal and the ScanShift signal. Each of the flip-flops receives a Serial In signal that cascades through the flip-flops to produce a Serial Out signal. In addition, each scan-flop
15
receives a pseudo-output from combinational logic, and produces a pseudo-input that is coupled to the combinational logic. The combinational logic also receives primary inputs and produces primary outputs.
A tester or test controller loads/unloads the internal states on the scan-path directly via the scan interface formed by the two data pins, Serial In and Serial Out, and a control terminal, the ScanShift signal. An ATPG program can treat the state elements as pseudo inputs and outputs of the device. During testing, the scan-path itself is first tested by shifting a simple sequence of 1s and 0s through the chained scan-flops. The ATPG program then generates test vectors that are applied to test the combinational logic, as shown, for example, in the timing diagram of FIG.
3
. The input values assigned to the pseudo-inputs in a test vector are serially loaded into the state elements via the scan-path, while those assigned to primary input pins are directly applied to those pins. The device then returns to normal operational mode, typically for one clock cycle, to capture the response of the combinational circuit in the scan-flops. The captured response is unloaded via the scan-path and, at the same time, the state element values corresponding to the next test vector are loaded. This testing sequence repeats until all test vectors are applied.
The scan-flop shown in
FIGS. 1 and 2
are often called Data-Mux type scan-flops. In this type of scan-flop, both the normal operation and the scan shift operation use a common clock, thus only requiring a single global clock to be distributed throughout the device under test (“DUT”). In addition, the ScanShift control signal must be routed throughout the chip being tested. Some scan tests require that the scan operation be performed at the full clock speed of the integrated circuit. Thus, if the device under test is a processor operating at 1 GHz to identify certain operational errors, the scan test must be performed at 1 GHz. Because the Data-Mux type scan-flops run at the internal clock speed, the scan-path comprising the Data-Mux type scan-flops can be easily designed to operate at the full clock speed. Problems arise, however, when interfacing the high speed scan-path with the external test equipment, which must match the high rate of data transfer through the scan-path. This significantly increases the complexity and cost of the test equipment, as well as the fixtures and accessories required for testing.
One common solution to this problem is shown in
FIG. 4
, in which parallel-in/serial-out (“PISO”) registers are used to convert parallel input data to serial data, and conversely, serial-in/parallel-out (“SIPO”) registers are used to convert the serial output of the scan register to a parallel output. The PISO registers and SIPO registers therefore are used to throttle input signals from a slower test device to a higher speed device under test, and to throttle down test results from the device under test to the test device. Thus, for example, a 1 GHz device under test may receive
10
parallel input signals from a 100 MHz tester. The
10
input signals, received at 100 MHz, are received in the PISO and converted to
1
GHz serial signals to be successively applied to a serial input terminal of the device under test. The 1 GHz signals on the serial output pin are converted to
10
parallel signals in the SIPO register, where the signals are clocked out at 100 MHz. The main problem with this technique is that it requires many input and output terminals on the device under test to implement. In the example above, 10 input pins and 10 output pins are required to effectively provide a single serial input and a single serial output for testing. Needless to say, the overhead associated with configuring a device under test to accept this number of test pins can be prohibitive.
It would be advantageous if a technique could be developed for testing high speed electronic circuits with slower speed test equipment, without requiring a large number of terminals on the device under test to be used for interfa
Bhavsar Dilip K.
Lang Steve
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