Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-10-19
2001-08-07
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S721000
Reexamination Certificate
active
06272657
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the field of digital CMOS devices, and more specifically to an apparatus and method for verifying electrical parameters of the I/O drivers of an integrated circuit.
BACKGROUND ART
While an integrated circuit (IC) may have been thoroughly tested before being assembled onto a printed circuit board, a board level test is usually still needed to verify that the IC has not been damaged during assembly, for example, by electrostatic discharge which may destroy the driver (buffer) coupled to an input/output pad. It is also necessary to test at the board level to ensure that there are no shorts or open circuits on the I/O pads.
Typically, a single power bus provides power to all of the I/O drivers. It is therefore important to test the power distribution among the drivers to ensure they perform adequately. A parametric test is an indispensable item in making such a determination. In the parametric test, electric characteristics (e.g., input and output current characteristics) of peripheral cells such as input and output buffers, provided on the periphery of a logic device, are tested.
Known methods of testing for these failures generally involve providing a complex, time consuming, set of patterns to get the logic on the pads to desired states for testing purposes. For example, it is known to provide a serial scan path through an integrated circuit device for testing purposes. A carefully designed sequence of data is driven through the serial scan path to test logic functions. Other approaches require additional external pins to put the device in a test mode. This approach is wasteful of pins, since these tests typically either take place only during the manufacturing process and/or are performed infrequently.
Boundary scan techniques also have been developed to address this issue. A boundary scan-capable device has the following structure: A peripheral cell area of an IC chip includes memory circuits for use in test, each connected to a signal line connected to an external terminal. The memory circuits are connected to each other, resulting in a shift register which serves as a testing structure. With such IC chips mounted on a board, a functional test is performed by utilizing the testing structure. Each of the IC chips has a data input terminal, a data output terminal, and a test control terminal. The terminals of the IC chips are connected so as to perform a desired test. Data for use in a test is serially input through the data input terminal of an IC chip, subjected to a serial shift operation by a control signal, and serially output through the data output terminal. In this manner, data can be written in and read out from memory circuits. In other words, the serial shift operation of the test data allows an individual test for each of the IC chips. However, devices which incorporate boundary scan circuitry increase the unit cost of the device, and more significantly such circuitry consumes valuable silicon real estate.
What is needed is a way to test the I/O drivers on IC pads at the board level without requiring complex test patterns. There is a need to provide parametric test within a few vectors on a tester. It is desirable to provide such testing with a minimal requirement of IC silicon. There is also a need to provide an I/O pad testing scheme without having to define additional dedicated pins on the chip.
SUMMARY OF THE INVENTION
An IC device having parametric testing capability includes core logic, input and output drivers, coupling circuitry associated with each of the inputs to the core logic, and selector circuitry associated with each of the outputs from the core logic. Each of the coupling circuitry and selector circuitry has first and second inputs and an output. Each input to the core logic is coupled to the first input of its associated coupling circuit. Each output from the core logic is coupled to the first input of its associated selector circuit. The coupling and selector circuitry are connected to form a single test chain, wherein the output of each coupling circuit feeds into the second input of another coupling circuit or a selector circuit, and wherein the second input of each selector circuit is coupled to the second input of another selector circuit or a coupling circuit.
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Atmel Corporation
McGuire, Jr. John P.
Schneck Thomas
Torres Joseph D.
Tu Christine T.
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