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Compressing test responses using a compactor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Compressing test responses using a compactor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Compressing test responses using a compactor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Computer program product for performing testing of a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Computer program product for performing testing of a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Computer-aided design (CAD) multiple-capture DFT system for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Computer-readable recording medium storing a method of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Computerized automation system and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Concurrently programmable dynamic memory built-in self-test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Configurable IC with error detection and correction circuitry

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Configurable integrated circuit and method of testing the same

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Configurable memory architecture with built-in testing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Configurable memory design for masked programmable logic

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Configurable scan path structure

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Configuration and method for storing the test results...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Configuration control in a programmable logic device using non-v

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Configuration for generating signal impulses of defined...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Configurator arrangement and approach therefor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Configuring flash memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Connecting analog response to separate strobed comparator...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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