Configurable memory architecture with built-in testing...

Details Configurable memory architecture with built-in testing... Configurable memory architecture with built-in testing...

2006-05-26

2009-10-13

Ellis, Kevin L (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000, C714S720000, C714S718000, C324S765010, C365S201000

Reexamination Certificate

active

07603603

ABSTRACT:
A configurable memory architecture includes a built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced overhead, in terms of area and speed. Memories can fail at high speed due to glitches (unwanted pulses which can at times behave as invalid clocks and destroy the functionality of synchronous systems) produced in decoding, the slow precharge of bitlines or the slow sensing of the sense amplifiers. The memory architecture incorporates structured DFT techniques to separately detect these failures.

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