Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-09-16
2002-02-19
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S725000, C324S1540PB
Reexamination Certificate
active
06349395
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit and a method of testing the same. In particular, the present invention relates to an integrated circuit having configurable logic blocks (CLBs) that are configurable according to external signals and a method of testing such an integrated circuit.
2. Description of the Related Art
Integrated circuits having CLBs that are configurable according to external signals are flexible to use, and therefore, their demand is increasing.
The integrated circuits having CLBs, however, involve low packaging density and slow operation speed. Accordingly, they have never been used in fields where high packaging density and high operation speed are important.
FIG. 1A
roughly shows a CLB
1
and a CLB memory
3
according to a prior art. The CLB memory
3
stores data for configuring the CLB
1
. The prior art provides each CLB with a CLB memory. If many CLBs each having a CLB memory are installed in an integrated circuit, the CLB memories occupy a large area in the integrated circuit.
FIGS. 2A and 2B
show an example of the structure of a CLB according to a prior art. The CLB consists of 2- or 4-input multiplexers (MUXs)
21
,
23
,
25
,
27
, and
29
. Each of the 2-input multiplexers receives a selection signal to select one of two inputs and outputs the selected one. Each of the 4-input multiplexers receives two selection signals to select one of four inputs and outputs the selected one.
The multiplexers are connected to one another, and the selection signals are changed so that the multiplexers may realize the function of a logic block such as an AND, NAND, OR, NOR, or EXOR logic block.
The selection signals to the multiplexers and connection lines between the multiplexers are programmable according to configuration data stored in the CLB memory
3
. Namely, the CLB memory
3
must have all data necessary for selecting inputs to the multiplexers
21
to
29
and determining connections between the multiplexers. As a result, the CLB memory
3
needs a large area.
The integrated circuits having CLBs are optionally configurable by a user, and therefore, are advantageous in shortening a development period of electronic devices that involves trial and error and functional modifications. The integrated circuits having CLBs are also applicable to electronic devices that are manufactured in small quantities. Some integrated circuits having CLBs allow a user to configure some CLBs without affecting other CLBs that are operating.
In contrast with the CLBs that have the above-mentioned problems of low packaging density and slow operation speed, hard-wired logic blocks (HLBs) consisting of fixed elements and wires achieve high packaging density. For example, an HLB serving as a 2-input NAND gate is made of only four transistors. On the other hand, a CLB serving as a 2-input NAND gate must have many multiplexers and inverters as shown in FIG.
2
A. In addition, the CLB must have a CLB memory. It is said that the packaging density of CLBs is one tenth or below of that of HLBs.
In connection with the operation speed, the HLB serving as a 2-input NAND gate involves a single gate stage to pass signals therethrough. On the other hand, the CLB of
FIG. 2
involves many multiplexers and inverters to pass signals therethrough, to elongate a signal transmission time. It is said that the operation speed of CLBs is one tenth or less of that of HLBs.
Due to these problems, it is difficult to apply CLBs to fields where packaging density and operation speed are important.
Another problem of CLBs is difficulty in testing them because they are configurable.
FIG. 1B
shows a method of testing a CLB according to a prior art. The CLB is a reconfigurable function unit (RFU) that is configured according to external data SO into, for example, a parallel multiplier. Data X and Y for a multiplication are supplied to the RFU, which provides a resultant output Z. The output Z is examined by a tester to determine whether or not the RFU is sound.
This testing method needs a large number of combinations of input vectors X and Y and many output pins to verify each output Z. When verifying the output Z, the tester must secure high-speed operation corresponding to the internal operation frequencies of the RFU. These factors complicate the testing of CLBs.
SUMMARY OF THE INVENTION
An object of the present invention is to improve the packaging density and operation speed of an integrated circuit having CLBs that are configurable according to external signals, and make the testing of the integrated circuit easier.
In order to accomplish the objects., the present invention provides an integrated circuit having CLBs that share configuration data stored in a configuration memory, to reduce the number of configuration memories and improve packaging density.
The present invention employs, if possible, HLBs to improve the packaging density and operation speed of the integrated circuit.
The present invention reconfigures connections among the CLBs and HLBs according to block-connection data. The present invention connects the CLBs and HLBs to form logic-block sets that share block-connection data, thereby reducing the number of memories necessary for storing block-connection data and improving the packaging density.
The present invention may combine the logic-block sets into partial circuits whose connections are reconfigurable.
The present invention symmetrically arranges CLBs with respect to a CLB memory, to equalize the lengths of wires to the CLBs.
The present invention provides CLBs with the same configuration data and the same test data and compares operation results provided by the CLBs with one another, to easily test the CLBs.
Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing the invention in practice.
REFERENCES:
patent: 4695740 (1987-09-01), Carter
patent: 5336950 (1994-08-01), Popli et al.
patent: 5432441 (1995-07-01), El-Ayat et al.
patent: 5481696 (1996-01-01), Lomp et al.
patent: 5991907 (1999-11-01), Stroud et al.
patent: 6003150 (1999-12-01), Stroud et al.
patent: 6069489 (2000-05-01), Iwanczuk et al.
patent: 0497029 (1992-08-01), None
patent: 6-90597 (1994-11-01), None
patent: 9938071 (1999-07-01), None
Ethan Mirsky, et al., IEEE Symposium on FPGAs for Custom Computing Machines. “Matrix: a Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources”, Apr. 17-19, 1996.
Fujii Hiroshige
Ohuchi Kazunori
Oowaki Yukihito
Sekine Masatoshi
Yoshida Masako
Kabushiki Kaisha Toshiba
Moise Emmanuel L.
LandOfFree
Configurable integrated circuit and method of testing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Configurable integrated circuit and method of testing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Configurable integrated circuit and method of testing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2939505