Configurable memory design for masked programmable logic

Details Configurable memory design for masked programmable logic Configurable memory design for masked programmable logic

2006-02-14

2006-02-14

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07000165

ABSTRACT:
A mask programmable integrated circuit includes a read only memory (ROM), a random access memory (RAM), and a controller. The controller couples to the ROM and RAM. The controller senses a reset condition and, in response, directs a clear of the RAM or a preload of contents of the ROM to the RAM. The preload can be performed after a successful self-test of the RAM is achieved. The RAM has a variable word length and depth size and can be configured to operate in one of many modes. The integrated circuit further includes a first and a second multiplexer (MUX). The first MUX is interposed between the RAM and the ROM, and selectively couples either the ROM data or the built-in self-test (BIST) data to the first MUX output. The second MUX is interposed between the first MUX and the RAM, and selectively couples either the output of the first MUX or a (synchronous or asynchronous) data input to the RAM. With the preload feature, the invention can emulate a ROM, a preloaded RAM, or look-up table logic functions as well as conventional RAM. Further, BIST allows for testing of the RAM without the needs for external support.

REFERENCES:
patent: 3829842 (1974-08-01), Langdon et al.
patent: 4439764 (1984-03-01), York et al.
patent: 4609838 (1986-09-01), Huang
patent: 4812627 (1989-03-01), Wexler et al.
patent: 4852073 (1989-07-01), Shinohara et al.
patent: 4967155 (1990-10-01), Magnuson
patent: 5041964 (1991-08-01), Cole et al.
patent: 5105425 (1992-04-01), Brewer
patent: 5526278 (1996-06-01), Powell
patent: 5526678 (1996-06-01), Shaw et al.
patent: 5936868 (1999-08-01), Hall
patent: 6065134 (2000-05-01), Bair et al.
patent: 6066960 (2000-05-01), Pedersen
patent: 6154837 (2000-11-01), Fudeyasu et al.
patent: 6233191 (2001-05-01), Gould et al.
patent: 6249143 (2001-06-01), Zaveri et al.
patent: 6492833 (2002-12-01), Asson et al.
Altera 1996 Data Book pp. 93-118.
Altera Corporation, “FLEX 10K Embedded Programmable Logic Family”, Data Sheet, Jul. 1995.
Altera Corporation, “Implementing RAM Functions in FLEX 10K Devices”, Applicaiton Note 52, Nov. 1995.
Altera Corporation, “Implementing FIFO Buffers in FLEX 10K Devices”, Application Note 66, Jan. 1996.
Altera Corporation, “FLEX 8000 Programmable Logic Device Family”, Data Sheet, Jun. 1996.

Affiliated with

Also associated with

Rating

Configurable memory design for masked programmable logic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Configurable memory design for masked programmable logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Configurable memory design for masked programmable logic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3668456