Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-05-15
2007-05-15
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C370S251000
Reexamination Certificate
active
10796484
ABSTRACT:
A circuit testing approach involves configurable switch control for automatically detecting and routing test signals along a plurality of test circuit paths. According to an example embodiment of the present invention, a configurator arrangement (100) is programmed to control a configured circuit (110), the control including automatically setting switches (115) on the configured circuit. In one implementation, the configurator arrangement is programmed to automatically detect test signals (i.e., digital and/or JTAG test signals) and to control switches (115) for routing test data along a test circuit path. With this approach, manual switching for routing the test signals is not necessary, which has been found to be useful in applications where access to the circuit paths for switching is difficult or impossible. In another implementation, a communications link (130) passes signals between the configurator arrangement and a user interface (140), including control signals from the user interface and data from the configured circuit. The configurator arrangement (100) is further controllable (i.e., manually) or programmable by signals received from the user interface (140).
REFERENCES:
patent: 6425101 (2002-07-01), Garreau
patent: 6587979 (2003-07-01), Kraus et al.
patent: 6697967 (2004-02-01), Robertson
patent: 6834366 (2004-12-01), Kim et al.
Avery Daniel Lee
Bailey Joel Patrick
Pendley Randall
Smith Michael J.
NXP B.V.
Tu Christine T.
Zawilski Peter
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