Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-06-25
2000-10-17
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714 46, G01R 3128
Patent
active
06134690&
ABSTRACT:
Computerized system and method are provided which have particular utility in the field of automated testing. In one embodiment of the method of the present invention, an array is stored in computer-readable memory. The array has a plurality of tuples, each of which includes a respective action field, a respective expected result field, a respective success field, and a respective failure field. The respective action field is for specifying at least one respective action whose performance by the system-under-test is to be commanded. The respective reaction field is for specifying at least one respective expected result to be achieved by performance of the respective action. The respective success and failures fields are for specifying further appropriate actions to be executed if the respective expected result is achieved (i.e., if a success condition occurs), or if the respective expected result is not achieved (i.e., if a failure condition occurs). A processor generates a command to the system-under-test to perform the action specified by the action field of a beginning tuple. The processor then receives an indication of an actual result of execution of the command by system-under-test, and compares this actual result to the expected result specified in the reaction field of the beginning tuple in order to determine whether a success or failure condition has occurred. Based upon whether a success or failure condition is determined by the processor to have occurred, the further action specified in the success or failure fields is executed.
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Ivaturi Devi Prasad
Patel Kushal A.
Cady Albert De
Cisco Technology Inc.
Lamarre Guy
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