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Circuit including a built-in self-test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuit scan output arrangement

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuit state scan-chain, data collection system and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuit structure for testing microprocessors and test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuit test pattern edition apparatus, circuit test pattern...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuit testing with ring-connected test instrument modules

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuit testing with ring-connected test instrument modules

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuit timing monitor having a selectable-path ring oscillator

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuit to prevent inadvertent test mode entry

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuit with expected data memory coupled to serial input lead

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuitry for and system and substrate with circuitry for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuitry for handling high impedance busses in a scan...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuitry to prevent peak power problems during scan shift

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuitry with multiplexed dedicated and shared scan path cells

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuits and associated methods for improved debug and test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuits and methods for testing logic devices by modulating...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Circuits and methods for testing programmable logic devices...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Clock adjusting method and circuit device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Clock adjusting method and circuit device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Clock control circuit for test that facilitates an at speed...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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