Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-10-29
2001-06-19
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S739000, C714S727000
Reexamination Certificate
active
06249892
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a circuit structure and method for testing microprocessors and microcontrollers, and more particularly, to a circuit structure and method for testing microprocessors and microcontrollers in an IC chip or circuit board with substantially no increase in hardware overhead.
BACKGROUND OF THE INVENTION
Microprocessor and microcontroller (hereinafter “microprocessor”) testing is considered one of the most complex problem in IC testing. In general, an automatic test equipment (ATE) such as an IC tester is commonly used for testing a microprocessor. An IC tester provides a test pattern to the microprocessor under test and the resultant response of the microprocessor is evaluated by expected value data. Because the recent microprocessors have dramatically improved their performance, such as operating speeds, density, functionality, and pin counts, an IC tester for testing such microprocessors needs to be very large scale, high speed, and accordingly very expensive. For example, such an IC tester has several hundreds or more test pins (test channels), each of which includes a pattern generator, timing generator and a frame processor, resulting in a very large and high cost system.
In other approach, various design-for-test (DFT) and built-in self-test (BIST) schemes such as scan, partial scan, logic BIST, scan-based BIST are used to test various logic blocks within a microprocessor. The main problem in these approaches is the requirement of large amount of additional hardware area (extra logic circuits) to implement the test logic. For example, scan implementation in general requires approximately 10% area overhead and scan-based BIST requires approximately 10-15% area overhead on top of the scan implementation. This large area overhead causes larger die, which results into smaller number of dies per wafer, lower yield and higher cost.
In addition, these test schemes also cause a 5-10% performance penalty. Typically, such a performance penalty is a signal propagation delay in the microprocessor because of the additional hardware overhead in the microprocessor. For example, in the scan implementation, each flip-flop circuit in the microprocessor is preceded by a selector (multiplexer) to selectively provide the flip-flop either a scan-in signal or a normal signal. Such an additional selector causes a delay time in the overall performance of the flip-flop circuit. Thus, the design-for-test and built-in self-test schemes adversely affect the microprocessor's performance, such as an operating speed because of the signal propagation delays.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a method and structure for testing microprocessors without having the disadvantages involved in the conventional technologies.
It is another object of the present invention to provide a method and structure for testing microprocessors which require substantially no hardware overhead in the IC chip.
It is a further object of the present invention to provide a method and structure for testing microprocessors which involve no performance penalty in the microprocessors to be tested.
It is a further object of the present invention to provide a method and structure for testing microprocessors which are capable of testing the microprocessors with low cost and high efficiency.
In the present invention, three extra registers are added to the periphery of the microprocessor and random test patterns are provided to the microprocessor and the response of the microprocessor is compressed before being compared with the pre-computed signature.
The present invention, for testing a microprocessor having an instruction fetch unit, an instruction decoder, a system memory, and an instruction execution unit, is comprised of:
a test control register for providing instructions to the instruction decoder of the microprocessor during testing;
a first multiplexer for selecting either the test instructions from the test control register or instructions from the instruction fetch unit;
a linear feedback shift register for providing test operand to the instruction execution unit of the microprocessor;
a second multiplexer for selecting either the test operand from the linear feedback shift register or operand from the system memory;
a multi-input feedback shift register for receiving results from the instruction execution unit, and a controller for providing the test instruction to the test control register and the linear feedback shift register and evaluating an output signature of the multi-input feedback shift register.
Another aspect of the present invention is a method of testing a microprocessor which is comprised of the following steps of:
(a) activating a test mode;
(b) initializing a test control register, a linear feedback shift register, and a multi-input feedback shift register;
(c) loading the test control register with opcode (operation code) of a test instruction;
(d) providing contents of the test control register to the instruction fetch;
(e) clocking the linear feedback shift register and multi-input feedback shift register either for a fixed number of cycles or 2
N
-1 cycles, where N is a number of stages of the linear feedback shift register and multi-input feedback shift register;
(f) taking out contents (signature) of the multi-input feedback shift register;
(g) comparing the signature of the multi-input feedback shift register with pre-computed simulation signature to determine if there is a fault; and
(h) repeating the foregoing steps (a)-(g) with different instruction until all instructions are exercised.
The present invention does not require large area overhead, it requires only three registers, and causes no performance penalty. This method is applicable to both standard product microprocessors as well as embedded microprocessors, embedded cores, 2D/3D graphics accelerators, DSP (digital signal processor), audio/video, and multi-media chips.
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Rajsuman Rochit
Yamoto Hiroaki
Advantest Corp.
De'cady Albert
Lamarre Guy J.
Muranmatsu & Associates
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