Circuit including a built-in self-test

Details Circuit including a built-in self-test Circuit including a built-in self-test

2001-10-22

2004-12-28

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S728000

Reexamination Certificate

active

06836866

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the field of integrated circuits. The invention relates to a circuit including a built-in self-test, particularly, an integrated circuit in a chip card having improved testing capabilities.
Particularly for the logical testing of integrated circuits, conventional software tests are utilized for functional testing, or hardware tests are utilized for structural testing.
FIG. 4
is a schematic block circuit diagram of a prior art testing configuration for testing a complex circuit
1
with a conventional software test. In
FIG. 4
, the reference character ET refers to an external testing device that is in contact with the tested complex circuit
1
through a standard interface S
1
. The complex circuit
1
substantially includes a functional circuit FS, which serves, on one hand, for actuating an actual logic circuit LM, and, on the other hand, for the functional testing of the logic circuit LM. The functional circuit FS is connected to the logic circuit LM actually being tested through a direct interface S
2
, which essentially represents a connection to the inputs and outputs of the logic circuit LM. Typically, a test access through such a direct interface S
2
occurs only through registers, for which reason it is also referred to as a “software interface” or a “register interface”. To test the complex circuit
1
, the external testing device ET sends a variety of test data across the standard interface S
1
to the functional circuit FS, which performs a functional test of the logic circuit LM through the direct interface S
2
.
The disadvantage of such a conventional software test, wherein it is only possible to perform a functional test of the logic circuit LM, is the relatively small test coverage of approximately 60 to 70 percent. The coverage is essentially due to the fact that particular internal areas of the logic circuit LM cannot be reached by the conventional functional test.
Thus, to improve the test coverage, hardware tests have been developed, which are represented in FIG.
5
and FIG.
6
.
FIG. 5
is a schematic block diagram of another conventional prior art test configuration, with which it is possible to perform a structural test of a circuit by what is referred to as a hardware test. According to
FIG. 5
, the complex circuit
1
being tested substantially includes a logic circuit LM that is in contact with the outside environment through a standard interface S
1
. In contrast to the functional test represented in
FIG. 4
, in which the test is performed over the standard interface S
1
, the test configuration represented in
FIG. 5
additionally has a structural interface SS, which makes possible a structural testing of the logic circuit LM. To realize the structural interface SS, five additional terminal lines are usually required, which include an input and output terminal, a timing and control terminal, and a terminal for activating and deactivating the structural interface SS. The structural interface SS leads into internal areas of the logic circuit LM, making it possible to also reach the logic areas that are difficult to access for a conventional functional test. In the conventional test as represented in
FIG. 5
, optimized test patterns with respect to the specific technical characteristics of the logic circuit LM are calculated and fed to the logic circuit LM by the external test device ET by way of the structural interface SS. The response of the logic circuit LM to the test pattern is fed to the external test device by way of the structural interface SS and is processed there. As such, an extraordinarily high test coverage of up to 100% can be obtained by a small number of optimized test patterns.
A disadvantage of such a conventional testing technique is the additional structural interface SS, which, on one hand, poses security problems in sensitive circuits, and, on the other hand, represents additional hardware for operating the complex circuit
1
. Furthermore, a larger area is consumed by the complex circuit
1
for the hardware test.
FIG. 6
represents a schematic block diagram of a separate conventional prior art test configuration, wherein what is referred to as a Built-In Self-Test (BIST) is utilized to reduce the computing expenditure for determining the optimized test pattern as represented in FIG.
5
. The conventional test configuration represented in
FIG. 6
substantially corresponds to the conventional test configuration represented in
FIG. 5
, but the complex circuit
1
includes a built-in self-test (BIST) as the structural testing device ST. A standard interface S
1
is utilized to operate the logic circuit LM in such a case, also, while the built-in structural testing device ST is in contact with an external testing device ET by way of a simplified structural interface SS′. The BIST used in
FIG. 6
usually includes what is referred to as a pseudo-random number generator for the high-speed generation of test patterns. In an extremely simple fashion, the pseudo-random number generator generates a plurality of test patterns that are fed to the tested logic circuit LM by way of internal access points (scan path and/or test points), and the corresponding result test patterns are evaluated. The result vectors are expediently compressed in a non-illustrated signature register, and the signatures so obtained are compared to a desired value. Unlike the testing configuration represented in
FIG. 5
, these test patterns that are generated by the pseudo-random number generator are not optimal with respect to the logic circuit LM, and, therefore, have a typical test coverage of approximately 80 percent.
Besides the smaller test coverage, the existence of the additional structural interface SS′ is also disadvantageous because it similarly represents a security problem and requires an extraordinarily large area for the additional hardware (BIST) in the complex circuit
1
, which area amounts to up to 10 percent of the total space required for the complex circuit
1
.
Particularly in integrated circuits that are used in what are referred to as chip cards, the number of external terminals and interfaces represents a significant problem. Specifically, such chip cards already have a fixed standard interface including a fixed number of terminals, which cannot be modified. Furthermore, particularly in what are referred to as money cards, providing an additional interface creates an unacceptable security risk because unauthorized manipulations must be reliably deactivated at the actual logic circuit.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit including a built-in self-test that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that makes possible an easy improvement of the test coverage of a circuit given the utilization of a fixed external interface.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a built-in self-test circuit to be connected to an external device, the circuit including a logic circuit having a structure to be tested, a structural testing device for testing the structure of the logic circuit, a functional circuit connected to the structural testing device through an indirect interface, the functional circuit driving the logic circuit through a direct interface; the functional circuit receiving test commands from an external device through a standard interface, and the functional circuit at least partially forwarding the test commands to the indirect interface for indirectly driving the logic circuit.
In particular, it is possible to improve the test coverage for a tested logic circuit without utilizing an additional external interface by utilizing a structural testing device and an indirect interface for connecting the structural testing device to a functional circuit of the complex circuit.
Expediently, in accordance with another feature of the invention, the structural testing device has a sc

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