Circuit test pattern edition apparatus, circuit test pattern...

Details Circuit test pattern edition apparatus, circuit test pattern... Circuit test pattern edition apparatus, circuit test pattern...

2005-11-18

2008-11-11

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S732000

Reexamination Certificate

active

07451372

ABSTRACT:
An apparatus that edits a test pattern used in a circuit function test includes a generator that generates a regular pattern that includes a plurality of unit patterns, by inserting a redundant pattern into a test pattern, and a pattern number reduction editor that defines the regular pattern as one unit pattern in the circuit function test.

REFERENCES:
patent: 5345450 (1994-09-01), Saw et al.
patent: 6782501 (2004-08-01), Distler et al.
Volkerink et al., Packet-based Input Test Data Compression Techniques, Oct. 7-10, 2002, IEEE, pp. 154-163.

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