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Selectively debugging processor cores through instruction codes

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self learning signatures

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self programmable shared bist for testing multiple memories

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self test circuit for a semiconductor intergrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self test device and self test method for reconfigurable...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self verifying communications testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self-adaptive test program

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Self-adaptive test program

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self-diagnostic circuit and self-diagnostic method for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self-repairing integrated circuit and method of operating...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self-repairing of microprocessor array structures

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self-repairing redundancy for memory blocks in programmable...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self-repairing semiconductor device having a testing unit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self-resetting, self-correcting latches

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self-resetting, self-correcting latches

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self-synchronizing pseudorandom bit sequence checker

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self-timed AC CIO wrap method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Self-timed reliability and yield vehicle with gated data and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self-verification of configuration memory in programmable...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self-verification of configuration memory in programmable...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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