Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-08-14
2007-08-14
Tu, Christine T. (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S736000
Reexamination Certificate
active
11036630
ABSTRACT:
In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.
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Mark Moyer, Jeffrey Byme (Applicants), U.S. Appl. No. 10/676,494, filed Sep. 30, 2003, entitled “Continuous Self-Verify Of Configuration Memory in Programmable Logic Devices”.
Nguyen Chi
Singh Satwant
Wu Ann
Yew Ting
Lattice Semiconductor Corporation
Tu Christine T.
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