Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-03-19
2000-12-26
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
324 731, G01R 3128
Patent
active
061675458
ABSTRACT:
A method and software apparatus are provided for implementing a dynamically modifiable test flow for integrated circuit devices that adapts to the characteristics of each processed device lot. According to the method of the invention, a modified set of tests sufficient to ensure proper device function for a particular lot is performed, reducing test costs and increasing test capacity. The method and system of the invention periodically samples a predetermined sample number of devices using a full set of tests including a set of skippable tests. Depending upon the performance characteristics of the sample device group on the skippable tests, a number of skippable tests are skipped during a modified test flow. After a next set of devices is tested using the modified test flow, the full set of tests is again performed on another sample group, and the size and makeup of the modified test flow is adjusted according to the new results. A test summary logs the results of regular and skippable tests, providing user access to enable system modification according to desired acceptance quality levels.
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Mack Ronald J.
Statovici Mihai G.
Cady Albert De
Casey, Esq. Michael R.
Tachner, Esq. Adam H.
Ton David
Xilinx , Inc.
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