Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-12-13
2005-12-13
Chase, Shelly (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000, C714S030000, C714S041000
Reexamination Certificate
active
06976198
ABSTRACT:
An integrated circuit (IC) and methods of manufacturing and operating ICs. In one embodiment, the IC includes: (1) a plurality of interchangeable hard macrocells, (2) at least one programmable logic block (PLB), (3) a bus intercoupling said plurality and said at least one programmable logic block and (4) a self-repair program, associated with said at least one programmable logic block, that causes said PLB to test at least some of said plurality and place at least a functioning one of said plurality into an operational status.
REFERENCES:
patent: 5659551 (1997-08-01), Huott et al.
patent: 6532579 (2003-03-01), Sato et al.
patent: 6560740 (2003-05-01), Zuraski et al.
patent: 6691264 (2004-02-01), Huang
“Considerations When Implementing a Design that uses an Arm Hard Macrocell” Mar. 2001 Document No. Arm Dai 0088A.
Britt Cynthia
Chase Shelly
Hitt Gaines PC
LSI Logic Corporation
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