Self verifying communications testing

Details Self verifying communications testing Self verifying communications testing

2004-10-06

2008-08-05

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07409618

ABSTRACT:
A system and method for testing a device with multiple interfaces by generating a predetermined data pattern within the device, transmitting the pattern to a test analyzer, generating a second predetermined data pattern within the test analyzer, and simultaneously transmitting the second test pattern to the device where the second test pattern is verified. The first and second test patterns may be the same or different, depending on the application. Further, the transmit and receive paths may be tested separately and independently in addition to simultaneously.

REFERENCES:
patent: 5663967 (1997-09-01), Lindberg et al.
patent: 6961317 (2005-11-01), Abramovitch et al.
patent: 6993696 (2006-01-01), Tanizaki et al.
patent: 7127648 (2006-10-01), Jiang et al.

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