Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-10-21
2000-05-02
Tu, Trinh L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
324765, G01R 3128
Patent
active
060584963
ABSTRACT:
A method and apparatus for testing a semiconductor chip includes providing the semiconductor chip with a common input/output (I/O) or bidirectional I/O pad. The I/O pad is electrically coupled to an off-chip driver (OCD) and an off-chip receiver (OCR). The OCD, I/O pad, and OCR are combined in a common input/output (CIO) or bidirectional I/O configuration. The I/O pad is effectively open circuited by an external tester and a performance parameter of the IO circuits connected to the open circuited pad is tested.
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Gillis Pamela Sue
McCauley Kevin William
Prilik Ronald J.
Wheater Donald Lawrence
Woytowich, Jr. Francis
International Business Machines - Corporation
Leas James M.
Tu Trinh L.
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