Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-09-26
2002-04-02
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S073100
Reexamination Certificate
active
06367041
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related generally to semiconductor device testing and specifically to self-adaptive modification of testing procedures to optimize test completion speed without reducing test coverage.
2. Description of the Background Art
Semiconductor devices are typically fabricated in large lots on silicon wafers. The fabrication process includes various steps such as deposition, electron beam lithography, plasma etching, sputtering and other techniques well known to those skilled in the art of semiconductor fabrication. As with any manufacturing process, defects arise during semiconductor fabrication. These defects must be detected by the manufacturer before devices are delivered to customers.
There are generally three types of tests for detecting defects on semiconductor devices: DC parametric tests, AC parametric tests, and functional tests. DC parametric tests include measuring input currents, output signals, and power consumption of the semiconductor device. AC parametric tests include measuring propagation delay between input and output terminals, minimum clock pulse width, and maximum operating frequency of the semiconductor device. Functional tests include testing whether the semiconductor device functions as designed under prescribed operating conditions. Typically, a functional test is carried out by applying a test pattern to the input terminals and comparing the generated output signals with an expected pattern. Minimum or maximum power supply (Vdd) and input signals are normally used during functional tests to emulate the full range of operating conditions.
The purpose of testing integrated circuits is to guarantee with a desired degree of confidence that any device shipped to the customer will meet all of the data sheet specifications (functionality, speed, voltages, currents, reliability, etc.) over the specified set of operating conditions, and over the entire life of the device. As circuit complexity grows, full test coverage requires increasing testing costs due to the high number of tests and the time consumed to perform them. Devices including in-system programmable (ISP) circuitry, for which test signals must be input in serial fashion, have particularly high testing costs. An important engineering challenge is therefore to find a minimal set of tests that consistently passes only devices that meet predetermined quality assurance standards.
One possible approach is to drop tests that appear unnecessary, based upon a statistical test program query, due to a zero failure rate. Indeed, even a minimal set of tests performed on an entire lot of devices normally includes at least one test that is never failed. However, such tests are only consistently found in typical device lots; where process variations and flaws are present, no test result can be taken for granted. Consequently, tests cannot be dropped from a test flow without the unacceptable risk of shipping defective parts. Moreover, for different types of silicon material and integrated circuit devices, there are different subsets of “statistical never fail” tests, and it is therefore impractical to predetermine a set of such tests before testing of a given lot begins.
In the field of programmable logic devices such as Complex Programmable Logic Devices (CPLDs), to which a specific embodiment of the present invention pertains, tests are typically performed on every manufactured device to ensure proper performance of every device shipped to customers. However, as explained above, such thorough and straightforward testing requires significant time and expense. There is therefore a need in the art to provide a method and system for device testing that diminishes the time and expense presently required, without compromising quality assurance.
SUMMARY OF THE INVENTION
To address the shortcomings of the available art, the present invention provides a method and apparatus for designing and implementing a test program that adapts dynamically to the characteristics of a given plurality of devices, providing a modified set of tests sufficient to guarantee proper device function at a designated acceptance quality level (AQL), while reducing costs and increasing test capacity for a given amount of resources. The novel software apparatus provided by the present invention periodically samples a predetermined number of devices using a full set of tests including a subset of skippable tests, then determines which of the skippable tests are to be skipped, providing a modified test set for a predetermined number of additional devices. (The term “skippable test” is used herein to mean a test that may be skipped under certain circumstances.) If none of the tests are to be skipped, the modified test set is the same as the full test set. After a plurality of devices is tested with the modified test set, the full test flow is again performed on another sample number of devices, and the composition of the modified test flow may be re-adjusted according to the new results. A test summary, including the failed and skipped tests and the number of times each such event occurs, is logged in a test summary log, thereby enabling system modification during the process to guarantee an AQL. One embodiment provides a dynamically modifiable test program for the XC9500™ family of complex programmable logic devices (CPLDS) available from Xilinx, Inc., assignee of the present invention.
It is therefore an advantage of the present invention to provide a method and apparatus for testing a given lot of integrated circuit devices, the given lot including a plurality of sample devices and a remainder of devices, the method comprising the steps of: 1) providing a first plurality of device tests for testing the given lot of devices for proper function under predetermined operating conditions; 2) designating as skippable a subset of the first plurality of tests; 3) executing the first plurality of tests on the plurality of sample devices and recording a plurality of test results; 4) creating, in a manner depending upon the plurality of test results, a second plurality of device tests comprising a subset of the first plurality, the second plurality excluding a number (zero or more) of the skippable tests; and 5) executing the second plurality of tests on a number of remaining devices.
In another embodiment, the first plurality of tests is executed on another plurality of sample devices, and another plurality of test results is recorded. Based on these new test results, a new test flow is created by skipping another number of skippable tests, and the new test flow is performed on another set of devices. This series of steps can then be repeated until the entire lot has been tested.
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Mack Ronald J.
Statovici Mihai G.
Cartier Lois D.
Casey Michael R.
Tachner Adam H.
Ton David
Xilinx , Inc.
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