Self test circuit for a semiconductor intergrated circuit

Details Self test circuit for a semiconductor intergrated circuit Self test circuit for a semiconductor intergrated circuit

2006-11-01

2010-06-01

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S700000

Reexamination Certificate

active

07730374

ABSTRACT:
A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKB1is held in flip-flop circuit105synchronously with checking clock signal A1. Checking pattern signal PAT_A is held in flip-flop circuit104synchronously with checking clock signal A2. When the skew margin of clock signal CKA_IN and data signal DA_IN are checked, the checking signal TCKA of flip-flop circuit105is input instead of clock signal CKA_IN, and the checking signal TDA of flip-flop circuit104is input instead of clock signal DA_IN. The timing relationship between clock signal CKB7and checking timing signal A1and the timing relationship between clock signal CKB7and checking timing signal A2are controlled independently by timing control circuit109.

REFERENCES:
patent: 6661266 (2003-12-01), Variyam et al.
patent: 7138829 (2006-11-01), Dalvi
patent: 7246286 (2007-07-01), Hsieh
patent: 7315968 (2008-01-01), Nakamura et al.
patent: 7548105 (2009-06-01), Shrank et al.
patent: 2001/0009530 (2001-07-01), Maeda

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