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Simultaneous AC logic self-test of multiple clock domains

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Simultaneously driving a hardware device and a software...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Single board DFT integrated circuit tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Single event functional interrupt detection system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Single event upset tolerant microprocessor architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Single platform electronic tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Single platform electronic tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Single-ended transmission for direct access test mode within...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Single-pass methods for generating test patterns for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Single-pass methods for generating test patterns for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Single-pass, concurrent-validation methods for generating...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Skewed inverter delay line for use in measuring critical...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Skewed latch flip-flop with embedded scan function

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Slack-based transition-fault testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Smart capture for ATPG (automatic test pattern generation)...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Smart tester and method for testing a bus connector

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Snoopy test access port architecture for electronic circuits...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Snoopy test access port architecture for electronic circuits...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Soc-based core scan chain linkage switch

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Soft coding of multiple device IDs for IEEE compliant JTAG...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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