Skewed latch flip-flop with embedded scan function

Details Skewed latch flip-flop with embedded scan function Skewed latch flip-flop with embedded scan function

2005-07-19

2005-07-19

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C327S202000, C710S061000, C711S109000

Reexamination Certificate

active

06920595

ABSTRACT:
A flip-flop circuit with embedded scan capabilities uses a skewed latch to pull one end of the flip-flop either up or down while another end of the flip-flop is active. Further, the flip-flop is designed such that a data node and a scan node are coupled to a master stage, which contains the skewed latch. The data node and scan node values are initially generated from different ends of the flip-flop. Based upon clock dependencies and whether the flip-flop is in a normal mode or a scan mode, the master stage passes a value to a slave stage dependent upon the data node and scan node values. Thereafter, the slave stage outputs a result based on the value passed from the master stage.

REFERENCES:
patent: 5920575 (1999-07-01), Gregor et al.
patent: 6150861 (2000-11-01), Matsunaga et al.
patent: 2002/0112208 (2002-08-01), Kakizawa et al.

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