Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-06-12
2007-06-12
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S025000, C714S032000
Reexamination Certificate
active
10908146
ABSTRACT:
A single-pass method for generating test patterns for sequential circuits operates upon an iterative array of time-frames representing the circuit. A mapping function is inserted at the end of each time-frame. Fault objects arriving at circuit next-state lines are mapped into good next-state fault objects and are placed onto corresponding present-state lines for a next time-frame. The good next-state mapping permits fault-propagation and path-enabling function size to be bounded by a size established during an initial time-frame. Path-enabling functions created during the initial time-frame are saved and are reused during subsequent time-frames. A search for test patterns continues from one time-frame to a next until a valid test pattern is found for each detectable fault.
REFERENCES:
patent: 5377197 (1994-12-01), Patel et al.
patent: 5430736 (1995-07-01), Takeoka et al.
patent: 5502729 (1996-03-01), Nakata
patent: 5588008 (1996-12-01), Nakata
patent: 5590135 (1996-12-01), Abramovici et al.
patent: 5831996 (1998-11-01), Abramovici et al.
patent: 5910958 (1999-06-01), Jay et al.
patent: 5933633 (1999-08-01), Good et al.
patent: 6018813 (2000-01-01), Chakradhar et al.
patent: 6141630 (2000-10-01), McNamara et al.
patent: 6195776 (2001-02-01), Ruiz et al.
patent: 6209120 (2001-03-01), Kurshan et al.
patent: 6282681 (2001-08-01), Sun et al.
patent: 6292915 (2001-09-01), Hosokawa et al.
patent: 6449743 (2002-09-01), Hosokawa
patent: 6789222 (2004-09-01), Buckley, Jr.
patent: 7017096 (2006-03-01), Abramovici et al.
Bergmann, J.P. etal., “Improving Coverage Analysis and Test Generation for Large Circuits,” IEEE 1999.
Bertacco, V., “Achieving Scalable Hardware Verification with Symbolic Simulation,” Ph.D. Dissertation, Stanford Univ., Aug. 2003, Ch. 3, pp. 43-66.
Bhatia, S. etal., “Integration of Hierarchical Test Generation with Behavioral Synthesis of Controller and Data Path Circuits,” IEEE Trans. VLSI Sys., vol. 6, No. 4, Dec. 1998.
Brace, K.S. etal., “Efficient Implementation of a BDD Package,” 27th ACM/IEEE Des. Auto. Conf., 1990, pp. 40-45.
Bryant, R.E., “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE Trans. Comp., vol. C-35, No. 8, Aug. 1986, pp. 677-691.
Bryant, R.E., “Symbolic Boolean Manipulation with Ordered Binary-Decision Diagrams,” ACM Comp. Surveys, vol. 24, No. 3, Sep. 1992, pp. 292-318.
Chakravarty, S. etal., “Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits,” IEEE Trans. Comp., vol. 45, No. 10, Oct. 1996, pp. 1131-1140.
Chang, S-C. etal., “TAIR: Testability Analysis by Implication Reasoning,” IEEE Trans. Comp-Aided Des., vol. 19, No. 1, Jan. 2000, pp. 152-160.
Cheng, K-T., “Tutorial and Survey Paper: Gate-Level Test Generation for Sequential Circuits,” ACM Trans. Des. Auto. of Elec. Sys., vol. 1, No. 4, Oct. 1996, pp. 405-442.
Cheng, K-T., “Transition Fault Testing for Sequential Circuits,” IEEE Trans. Comp-Aided Des., vol. 12, No. 12, Dec. 1993, pp. 1971-1983.
Cheng, K-T. etal., “Generation of High Quality Tests for Robustly Untestable Path Delay Faults,” IEEE Trans. Comp., vol. 45, No. 12, Dec. 1996, pp. 1379-1392.
Cheng, K-T. etal., “Automatic Generation of Functional Vectors Using the Extended Finite State Machine Model,” ACM Trans. Des. Auto., vol. 1, No. 1, Jan. 1996, pp. 57-79.
Cheng, K-T. etal., “A Functional Fault Model for Sequential Machines,” IEEE Trans. Comp-Aided Des., vol. 11, No. 9, Sep. 1992, pp. 1065-1073.
Corno, F. etal., “Enhancing Topological ATPG with High-Level Information and Symbolic Techniques,” Int'l Conf. Comp. Des. 1998.
Das, D.K. etal., “Isomorph-Redundancy in Sequential Circuits,” IEEE Trans. Comp., vol. 49, No. 9, Sep. 2000, pp. 992-997.
Fujiwara, H., “A New Class of Sequential Circuits with Combinational Test Generation Complexity,” IEEE Trans. Comp., vol. 49, No. 9, Sep. 2000, pp. 895-905.
Fummi, F. etal., “A Hierarchical Test Generation Approach for Large Controllers,” IEEE Trans. Comp., vol. 49, No. 4, Apr. 2000, pp. 289-302.
Ghosh, I. etal., “Automatic Test Pattern Generation for Functional RTL Circuits Using Assignment Decision Diagrams,” Des. Auto. Conf. 2000.
Giraldi, J. etal., “EST: The New Frontier in Automatic Test-Pattern Generation,” 27th ACM/IEEE Des. Auto. Conf. 1990, pp. 667-672.
Hamzaoglu, I. etal., “Deterministic Test Pattern Generation Techniques for Sequential Circuits,” IEEE/ACM Int'l Conf. on CAD, 2000, pp. 538-543.
Hamzaoglu, I., etal, “New Techniques for Deterministic Test Pattern Generation,” Jour. Elec. Testing, vol. 15, Issue 1-2, Aug.-Oct. 1999, pp. 63-73.
Hsiao, M.S., etal, “Dynamic State Traversal for Sequential Circuit Test Generation,” ACM Trans. Des. Auto. of Elec. Sys., vol. 5, No. 3, Jul. 2000, pp. 548-565.
Hsu, Y-C., etal, “A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits,” IEEE Trans. Comp., vol. 45, No. 11, Nov. 1996, pp. 1312-1388.
Inoue, T., etal, “An Optimal Time Expansion Model Based on Combinational ATPG for RT Level Circuits,” Proc. 7th Asian Test Symp, Dec. 1998, pp. 190-197.
Inoue, T., etal, “Test Generation for Acyclic Sequential Circuits with Hold Registers,” Proc. Int'l Conf on CAD, 2000, pp. 550-556.
IP, C.N., “Simulation Coverage Enhancement Using Test Stimulus Transformation,” Proc. Int'l Conf on CAD, 2000, pp. 127-134.
Kocan, F., etal, “Concurrent D-Algorithm on Reconfigurable Hardware,” Proc. Int'l Conf on CAD, 1999, pp. 152-156.
Langevin, M., etal, “Behavioral Verification of an ATM Switch Fabric Using Implicit Abstract State Enumeration,” Proc. 1996 Int'l Conf Comp Des, pp. 20-26.
Lin, X., etal, “Techniques for Improving the Efficiency of Sequential Circuit Test Generation,” Proc. 1999 Int'l Conf CAD, pp. 147-151.
Lin, X., etal, “On Finding Undetectable and Redundant Fautls in Synchronous Sequential Circuits,” 1998 Int'l Conf Comp Des.
Moundanos, D., etal, “Abstraction Techniques for Validation Coverage Analysis and Test Generation,” IEEE Trans. Comp., vol. 47, No. 1, Jan. 1998, pp. 2-14.
Ochi, H., etal, “Breadth-First Manipulation of Very Large Binary-Decision Diagrams,” Proc. Int'l Conf CAD, Nov. 1993, pp. 48-55.
Pomeranz, I., etal, “Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements,” 7th Asian Test Symp, Dec. 1998, pp. 446-451.
Pomeranz, I., etal, “A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination,” 7th Asian Test Symp, Dec. 1998, pp. 486-491.
Psarakis, M., etal, “Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays,” IEEE Trans. Comp., vol. 49, No. 10, Oct. 2000, pp. 1083-1099.
Stephan, P., etal, “Combinational Test Generation Using Satisfiability,” IEEE Trans. CAD, vol. 15, No. 9, Sep. 1996, pp. 1167-1176.
Sun, X., etal, “Functional Verification Coverage vs. Physical Stuck-at Fault Coverage,” 1198 Int'l.Symp Defect Fault Tol VLSI, pp. 108-116.
Tafertshofer, P., etal, “SAT Based ATPG Using Fast Justification and Propagation in the Implication Graph,” 1999 Int'l Conf CAD, pp. 139-146.
Tekumalla, R.C., etal, “On Primitive Fault Test Generation in Non-Scan Sequential Circuits,” 1998 Int'l Conf CAD, pp. 275-282.
Tragoudas, S., etal, “ATPG Tools for Delay Faults at the Functional Level,” ACM Trans. Des. Auto. Elec. Sys., vol. 7, No. 1, Jan. 2002, pp. 33-57.
Van Der Linden, J.T. etal., “Complete Search In Test Generation for Industrial Circuits with Improved Bus-Conflict Detection,” 7th Asian Test Symp., Dec. 1998, pp. 212-221.
Williams, T.W., “The New Frontier for Testing: Nano Meter Technologies,” 7th Asia
Buckley Robert
De'cady Albert
Trimmings John
Yardstick Research, L.L.C.
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