Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-04-25
2006-04-25
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S734000, C714S735000, C324S073100, C324S765010
Reexamination Certificate
active
07036062
ABSTRACT:
A design for test focused tester has a single printed circuit board tester architecture. By focusing on design for test testing and eliminating functional testing, the design for test focused tester reduces or eliminates requirements for high speed, precision signal formatting and timing circuitry that require a multiple board architecture interconnected via a high speed backplane. The single board architecture places a vector sequencer and vector memory close to the device under test, which provides short, consistent signal paths to the device and eliminates the need for dead cycles and synchronization between tester boards.
REFERENCES:
patent: 5260947 (1993-11-01), Posse
patent: 5654971 (1997-08-01), Heitele et al.
patent: 5899961 (1999-05-01), Sundermann
patent: 5948115 (1999-09-01), Dinteman
patent: 6826721 (2004-11-01), Williamson et al.
Kellerman David S.
Levy Andrew H.
Limaye Ajit M.
Morris Steven R.
Abraham Esaw
De'cady Albert
Klarquist & Sparkman, LLP
Teseda Corporation
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