Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-10-17
2006-10-17
Ton, David (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S744000
Reexamination Certificate
active
07124342
ABSTRACT:
A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, each scan chain comprising multiple scan cells coupled in series, each clock domain having one capture clock, each cross-clock domain block comprising a combinational logic network. The method comprises compiling the scan-based integrated circuit into a sequential circuit model; specifying input constraints on the scan-based integrated circuit during a shift and capture operation; specifying a clock grouping to map the N clock domains into G clock domain groups, where N>G>1; transforming the sequential circuit model into an equivalent combinational circuit model according to the input constraints and the clock grouping; and generating the stimuli and test responses on the equivalent combinational circuit model according to the input constraints.
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Abdel-Hafez Khader S.
Sheu Boryau (Jack)
Wang Laung-Terng
Wang Shun-Miin (Sam)
Wen Xiaoqing
Syntest Technologies, Inc.
Ton David
Zegeer Jim
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