Soc-based core scan chain linkage switch

Details Soc-based core scan chain linkage switch Soc-based core scan chain linkage switch

2007-11-13

2007-11-13

Lamarre, Guy (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S025000, C714S726000, C714S727000, C714S729000, C710S100000

Reexamination Certificate

active

10995099

ABSTRACT:
Disclosed herein is an SoC-based core scan chain linkage switch. The core scan chain linkage switch includes test bus terminals, scan chain input/output terminals, a switch unit and SCLK, UCLK, Mode and Enable signals. The test bus terminals apply instructions and input/output test data. The scan chain input/output terminals link with the scan chains of an embedded core. The switch unit completes a linkage configuration between the test bus terminals and the scan chain input/output terminals in response to the applied instructions. The SCLK, UCLK and Mode signals apply the instructions to dynamically reconfigure the switch unit and update the linkage configuration of the switch unit, and the Enable signal activates and deactivates the switch unit.

REFERENCES:
patent: 6324614 (2001-11-01), Whetsel
patent: 6324662 (2001-11-01), Haroun et al.
patent: 6425100 (2002-07-01), Bhattacharya
patent: 6425101 (2002-07-01), Garreau
patent: 6560734 (2003-05-01), Whetsel
patent: 6760874 (2004-07-01), Cote et al.
patent: 2002/0046375 (2002-04-01), Haroun et al.
patent: 2003/0126533 (2003-07-01), McAdams
Benabdenebi et al., “CAS-BUS: A Scalable and Reconfigurable Test Access Mechanisms for Systems on a Chip”, Mar. 27-30, 2000, IEEE Design Automation and Test in Europe Conference 2000, pp. 141-145.

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