Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-06-07
2011-06-07
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S741000
Reexamination Certificate
active
07958421
ABSTRACT:
A single-pass, concurrent validation method for generating test pattern sequences for sequential circuits maps fault objects arriving at circuit next-state lines into good next-state fault objects, and passes these mapped results to a next time-frame by placing the good next-state fault objects on present-state lines corresponding to the next-state lines at which to fault objects arrived. Path-enabling functions created during an initial time-frame are reused for all subsequent time-frames, permitting a fault-propagation size and a path-enabling function size to be bounded by a function size established during the initial time-frame. A valid test pattern sequence is found when a primary output line has a good output level that is a complement of a faulty output level for the line. In one embodiment, the determination and comparison of output levels is carried out concurrently.
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Buckley Robert
Gaffin Jeffrey A
Nguyen Steve
Yardstick Research, LLC
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