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On-chip scan clock generator for ASIC testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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On-chip service processor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip service processor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip service processor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip service processor for test and debug of integrated...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip stuck-at fault detector and detection method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip test apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-line fault tolerant operation via incremental...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-line partitioning for sequential circuit test generation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-line testing of field programmable gate array resources

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-line testing of the programmable interconnect network in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-line testing of the programmable logic blocks in field...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Optimized buffering for JTAG boundary scan nets

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Optimized JTAG interface

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Optimized JTAG interface

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Optimized JTAG interface

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Output stage of a multi-stage algorithmic pattern generator...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Over-voltage test for automatic test equipment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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