Optimized JTAG interface

Details Optimized JTAG interface Optimized JTAG interface

2011-03-01

2011-03-01

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000

Reexamination Certificate

active

07900110

ABSTRACT:
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

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“Synchronizing the IEEE 1149.1 test access port for chip level testability” by Bhavsar, This paper appears in: Design & Test of Computers, IEEE Publication Date: Apr.-Jun. 2000 vol. 17, Issue: 2 On pp. 94-99 ISSN: 0740-7475 INSPEC Accession No. 6611672.

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