On-chip scan clock generator for ASIC testing

Details On-chip scan clock generator for ASIC testing On-chip scan clock generator for ASIC testing

2011-07-05

2011-07-05

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000, C714S726000

Reexamination Certificate

active

07975197

ABSTRACT:
A scan clock generator includes a clock signal input for receiving a clock signal, a scan shift mode signal input for receiving a scan shift mode signal, and a sequence controller coupled to the clock signal input for gating a selected number of clock signal pulses at a time to generate a sequence of nonconcurrent scan clock signals at separate outputs respectively in response to a first state of the scan shift mode signal.

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patent: 6877123 (2005-04-01), Johnston et al.
patent: 2002/0138801 (2002-09-01), Wang et al.
patent: 2003/0204802 (2003-10-01), Sim
Wikipedia Online Encyclopedia. Multiplexer. 2005. http://en.wikipedia.org/wiki/Multiplexer.

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